Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

llvm-svn: 92873

for stack references.

llvm-svn: 92871

multiple register definitions.

llvm-svn: 92864

it work for any integer size return type.

llvm-svn: 92853

llvm-svn: 92850

(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.

llvm-svn: 92849

llvm-svn: 92841

llvm-svn: 92838

llvm-svn: 92837

phi nodes when deciding which pointers point to local memory.
I actually checked long ago how useful this is, and it isn't
very: it hardly ever fires in the testsuite, but since Chris
wants it here it is!

llvm-svn: 92836

llvm-svn: 92831

llvm-svn: 92830

memcpy, memset and other intrinsics that only access their arguments
to be readnone if the intrinsic's arguments all point to local memory.
This improves the testcase in the README to readonly, but it could in
theory be made readnone, however this would involve more sophisticated
analysis that looks through the memcpy.

llvm-svn: 92829

it on for darwin (it fails on linux).

llvm-svn: 92826

llvm-svn: 92824

bootstrap.

llvm-svn: 92818

synonyms for PPC.

llvm-svn: 92817

Previously, instcombine would only promote an expression tree to
the larger type if doing so eliminated two casts.  This is because
a need to manually do the sign extend after the promoted expression
tree with two shifts.  Now, we keep track of whether the result of
the computation is going to be properly sign extended already.  If
so, we can unconditionally promote the expression, which allows us
to zap more sext's.

This implements rdar://6598839 (aka gcc pr38751)

llvm-svn: 92815

An instruction like this:

  %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0

Must be replaced with this when substituting physical registers:

  %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>

llvm-svn: 92812

llvm-svn: 92810

llvm-svn: 92807

bottom-up scheduler. We prefer the lower order number.

llvm-svn: 92806

llvm-svn: 92800

test/CodeGen/X86, as doesn't use -indvars, and it does use
llc -march=x86-64.

llvm-svn: 92799

result in illegal types for the SHL operator.

llvm-svn: 92797

llvm-svn: 92796

llvm-svn: 92795

uses several kinds of opcode values which are not declared within
that enum. This fixes PR5946.

llvm-svn: 92794

llvm-svn: 92793

llvm-svn: 92792

llvm-svn: 92790

The only difference is that EvaluateInDifferentType checks to ensure
they are profitable before doing them :)

llvm-svn: 92788

llvm-svn: 92786

instructions.  Thumb does not have the restriction that t2 = t+1.

llvm-svn: 92785

llvm-svn: 92784

llvm-svn: 92783

llvm-svn: 92782

llvm-svn: 92781

It is enough to give the super registers CR0, CR1, ..., and specifying the
sub-registers as well causes confusion in the liveness computations.

llvm-svn: 92778

llvm-svn: 92777