llvm-svn: 122513

something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310

llvm-svn: 119990

llvm-svn: 119740

llvm-svn: 119098

First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place

llvm-svn: 119097

that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.

llvm-svn: 119056

value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167

llvm-svn: 114999

passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471

llvm-svn: 114461

SelectionDAG::getExtLoad overload, and eliminate it.

llvm-svn: 114446

llvm-svn: 114410

to try to re-use scavenged frame index reference registers. rdar://8277890

llvm-svn: 112241

Modernize predicates a bit.

The Predicate_* methods are not used by TableGen any longer. They are only
emitted for the sake of legacy code.

llvm-svn: 111263

llvm-svn: 111241

llvm-svn: 110460

llvm-svn: 110410

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

llvm-svn: 108567

llvm-svn: 108366

The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099

llvm-svn: 108086

llvm-svn: 107820

code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786

llvm-svn: 107710

the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691

llvm-svn: 107668

the pseudo instruction is not at the end of the block.

llvm-svn: 107655

Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.

llvm-svn: 107550

llvm-svn: 106466

llvm-svn: 106279

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

llvm-svn: 105322

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

This reverts commit 104654.

llvm-svn: 104660

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654

Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193