llvm-svn: 105108

llvm-svn: 105107

llvm-svn: 105106

llvm-svn: 105105

llvm-svn: 105104

Change RecordLayoutBuilder::LayoutNonVirtualBase to take a BaseSubobjectInfo. No functionality change.

llvm-svn: 105103

Move computing the base subobject info for a class into the RecordLayoutBuilder because we're going to need it to be able to correctly add offsets for primary virtual bases.

llvm-svn: 105102

shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.

llvm-svn: 105101

llvm-svn: 105100

llvm-svn: 105099

llvm-svn: 105098

llvm-svn: 105097

llvm-svn: 105096

llvm-svn: 105095

Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.

llvm-svn: 105092

llvm-svn: 105084

llvm-svn: 105083

llvm-svn: 105082

llvm-svn: 105066

llvm-svn: 105065

Also verify that all subregister indices compose unambiguously.

llvm-svn: 105064

were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063

valgrind problems.

llvm-svn: 105062

llvm-svn: 105061

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

llvm-svn: 105060

llvm-svn: 105059

Implement remaining items in neon td file.  Still need to modify emitter to generate a proper header.

llvm-svn: 105058

llvm-svn: 105014

llvm-svn: 105013

llvm-svn: 105012

(radar 8040068).

llvm-svn: 105011

llvm-svn: 105010

llvm-svn: 105009

as is done with most other cast opcode predicates.

llvm-svn: 105008

llvm-svn: 105007

llvm-svn: 105006

llvm-svn: 105005

llvm-svn: 105002

llvm-svn: 105001

align=native, at least for the platforms we support.

llvm-svn: 105000