Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.

Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.

llvm-svn: 74601

llvm-svn: 74597

llvm-svn: 74593

to not have to create a temporary vector (in the API at least).  Patch by Jay Foad!

llvm-svn: 74584

pic mode.

llvm-svn: 74582

Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.

llvm-svn: 74580

 - This more or less amounts to a revert of r65379. I'm curious to know what
   happened that caused this variable to become unused.

llvm-svn: 74579

llvm-svn: 74577

llvm-svn: 74574

llvm-svn: 74566

have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.

This allows for future work that would allow for precise no-op placement and the
like.

llvm-svn: 74564

llvm-svn: 74555

llvm-svn: 74551

in APIntTest.cpp.

llvm-svn: 74550

llvm-svn: 74549

Add 256-bit memory operand support.

llvm-svn: 74548

llvm-svn: 74543

llvm-svn: 74542

llvm-svn: 74537

Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.

llvm-svn: 74534

See http://msdn.microsoft.com/en-us/library/ms686818(VS.85).aspx

Patch by Olaf Krzikalla!

llvm-svn: 74526

This was caused by me confounding FP0 and ST(0).

llvm-svn: 74523

Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).

llvm-svn: 74519

Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.

The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518

llvm-svn: 74515

llvm-svn: 74510

llvm-svn: 74509

llvm-svn: 74508

llvm-svn: 74507

llvm-svn: 74500

llvm-svn: 74499

This will allow it to be used in unittests that use gtest's
EXPECT_EQ.

llvm-svn: 74494

llvm-svn: 74492

llvm-svn: 74491

 - Don't print "Parsing" in front of every message.

 - Take additional "type" argument which is prepended to the message (with ": ")
   if given.

 - Update clients to print errors (warnings) as:
<filename>:<line number>: error(warning): ...

llvm-svn: 74489

Add LLVMContext, which will eventually be used as a container for privatizing a lot of (currently) global state, including the
constant and type uniquing tables.  For now, just make it a wrapper around the existing APIs.

llvm-svn: 74488

llvm-svn: 74483

llvm-svn: 74482

llvm-svn: 74478

llvm-svn: 74477