llvm-svn: 25333

llvm-svn: 25312

flipped around.

llvm-svn: 25290

llvm-svn: 25278

llvm-svn: 25272

llvm-svn: 25261

llvm-svn: 25260

llvm-svn: 25259

llvm-svn: 25257

linked together).

llvm-svn: 25247

  LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.

llvm-svn: 25246

llvm-svn: 25232

llvm-svn: 25226

Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222

* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.

llvm-svn: 25207

llvm-svn: 25190

llvm-svn: 25188

llvm-svn: 25162

llvm-svn: 25160

llvm-svn: 25158

* FP cmp, setcc, etc.

llvm-svn: 25117

llvm-svn: 25105

inserted in the code.

llvm-svn: 25104

llvm-svn: 25103

llvm-svn: 25024

llvm-svn: 24990

llvm-svn: 24979

* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921

llvm-svn: 24919

bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917

  for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888

llvm-svn: 24877

llvm-svn: 24870

llvm-svn: 24768

llvm-svn: 24754

* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726

llvm-svn: 24631

llvm-svn: 24513

llvm-svn: 24438

llvm-svn: 24434