- Sep 11, 2012
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Chad Rosier authored
llvm-svn: 163649
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Chad Rosier authored
llvm-svn: 163648
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Chad Rosier authored
Add support in the EmitMSInlineAsmStr() function for handling integer consts. llvm-svn: 163645
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Manman Ren authored
a pair of switch/branch where both depend on the value of the same variable and the default case of the first switch/branch goes to the second switch/branch. Code clean up and fixed a few issues: 1> handling the case where some cases of the 2nd switch are invalidated 2> correctly calculate the weight for the 2nd switch when it is a conditional eq Testing case is modified from Alastair's original patch. llvm-svn: 163635
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Jakob Stoklund Olesen authored
Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
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Jakob Stoklund Olesen authored
Preserve the Composites map in the CodeGenSubRegIndex class so it can be used to determine which sub-register indices can actually be composed. llvm-svn: 163629
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Jakob Stoklund Olesen authored
Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. llvm-svn: 163628
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Chad Rosier authored
llvm-svn: 163627
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Nadav Rotem authored
Dragonegg selfhost exposed additional cases where alloca usage moved outside of lifetime markers. Disabling the pass for now. llvm-svn: 163623
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Nadav Rotem authored
llvm-svn: 163617
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Nadav Rotem authored
llvm-svn: 163616
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Evgeniy Stepanov authored
llvm-svn: 163612
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Duncan Sands authored
llvm-svn: 163601
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Craig Topper authored
llvm-svn: 163596
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Craig Topper authored
llvm-svn: 163594
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NAKAMURA Takumi authored
llvm-svn: 163593
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Alex Rosenberg authored
Add a pass that renames everything with metasyntatic names. This works well after using bugpoint to reduce the confusion presented by the original names, which no longer mean what they used to. llvm-svn: 163592
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Craig Topper authored
Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. Factor similar code out of FNEG DAG combiner. llvm-svn: 163587
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Chandler Carruth authored
Patch by Brad Smith! llvm-svn: 163584
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Andrew Trick authored
The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. llvm-svn: 163580
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Andrew Trick authored
llvm-svn: 163579
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Eric Christopher authored
right now. We'll fix PR13303 a different way. llvm-svn: 163570
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Eric Christopher authored
llvm-svn: 163569
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Eric Christopher authored
llvm-svn: 163568
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Eric Christopher authored
llvm-svn: 163567
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Chad Rosier authored
llvm-svn: 163565
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Chad Rosier authored
llvm-svn: 163561
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Chad Rosier authored
llvm-svn: 163557
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Chad Rosier authored
llvm-svn: 163556
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NAKAMURA Takumi authored
test/CodeGen/X86/ms-inline-asm.ll: Relax for non-darwin x86 targets. '##InlineAsm' could not be seen in other hosts. llvm-svn: 163554
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- Sep 10, 2012
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Chad Rosier authored
and InlineAsmVariant don't match. llvm-svn: 163550
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Chad Rosier authored
llvm-svn: 163549
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Dmitri Gribenko authored
llvm-svn: 163547
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Nadav Rotem authored
llvm-svn: 163545
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Chad Rosier authored
and update the printOperand() function accordingly. llvm-svn: 163544
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Chad Rosier authored
llvm-svn: 163542
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Nadav Rotem authored
llvm-svn: 163539
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Jakob Stoklund Olesen authored
The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> llvm-svn: 163535
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Michael J. Spencer authored
llvm-svn: 163532
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Nadav Rotem authored
llvm-svn: 163530
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