llvm-svn: 163649

llvm-svn: 163648

Add support in the EmitMSInlineAsmStr() function for handling integer consts.

llvm-svn: 163645

a pair of switch/branch where both depend on the value of the same variable and
the default case of the first switch/branch goes to the second switch/branch.

Code clean up and fixed a few issues:
1> handling the case where some cases of the 2nd switch are invalidated
2> correctly calculate the weight for the 2nd switch when it is a conditional eq

Testing case is modified from Alastair's original patch.

llvm-svn: 163635

Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

llvm-svn: 163630

Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.

llvm-svn: 163629

Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.

llvm-svn: 163628

llvm-svn: 163627

Dragonegg selfhost exposed additional cases where alloca usage moved outside of lifetime markers. Disabling the pass for now.

llvm-svn: 163623

llvm-svn: 163617

llvm-svn: 163616

llvm-svn: 163612

llvm-svn: 163601

llvm-svn: 163596

llvm-svn: 163594

llvm-svn: 163593

Add a pass that renames everything with metasyntatic names. This works well after using bugpoint to reduce the confusion presented by the original names, which no longer mean what they used to.

llvm-svn: 163592

Teach DAG combiner to constant fold FABS of a BUILD_VECTOR of ConstantFPs. Factor similar code out of FNEG DAG combiner.

llvm-svn: 163587

Patch by Brad Smith!

llvm-svn: 163584

The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

llvm-svn: 163580

llvm-svn: 163579

right now. We'll fix PR13303 a different way.

llvm-svn: 163570

llvm-svn: 163569

llvm-svn: 163568

llvm-svn: 163567

llvm-svn: 163565

llvm-svn: 163561

llvm-svn: 163557

llvm-svn: 163556

test/CodeGen/X86/ms-inline-asm.ll: Relax for non-darwin x86 targets. '##InlineAsm' could not be seen in other hosts.

llvm-svn: 163554

and InlineAsmVariant don't match.

llvm-svn: 163550

llvm-svn: 163549

llvm-svn: 163547

llvm-svn: 163545

and update the printOperand() function accordingly.

llvm-svn: 163544

llvm-svn: 163542

llvm-svn: 163539

The ARM backend can eliminate cmp instructions by reusing flags from a
nearby sub instruction with similar arguments.

Don't do that if the sub is predicated - the flags are not written
unconditionally.

<rdar://problem/12263428>

llvm-svn: 163535

llvm-svn: 163532

llvm-svn: 163530