series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27118

Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.

llvm-svn: 27117

llvm-svn: 27116

llvm-svn: 27115

llvm-svn: 27112

llvm-svn: 27109

llvm-svn: 27108

 <int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.

llvm-svn: 27106

llvm-svn: 27103

llvm-svn: 27102

llvm-svn: 27100

llvm-svn: 27096

llvm-svn: 27095

llvm-svn: 27094

llvm-svn: 27091

llvm-svn: 27089

llvm-svn: 27088

llvm-svn: 27087

llvm-svn: 27083

llvm-svn: 27081

llvm-svn: 27080

llvm-svn: 27079

llvm-svn: 27077

llvm-svn: 27076

llvm-svn: 27073

llvm-svn: 27071

llvm-svn: 27070

llvm-svn: 27069

modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll

llvm-svn: 27068

llvm-svn: 27065

llvm-svn: 27064

llvm-svn: 27063

comment.

This fixes 177.mesa, and McCat/09-vor with the td scheduler.

llvm-svn: 27060

Regression/CodeGen/PowerPC/vec_zero.ll

llvm-svn: 27059

llvm-svn: 27056

using a splat for {1.0,1.0,1.0,1.0}

llvm-svn: 27055

llvm-svn: 27053

llvm-svn: 27052

llvm-svn: 27051