llvm-svn: 101248

llvm-svn: 101247

llvm-svn: 101246

llvm-svn: 101245

llvm-svn: 101244

llvm-svn: 101243

llvm-svn: 101241

incompatibility with some clients covered by the buildbots, such as llvm-gcc.

llvm-svn: 101237

llvm-svn: 101234

llvm-svn: 101233

have been removed in r101231.

llvm-svn: 101232

llvm-svn: 101231

llvm-svn: 101230

llvm-svn: 101229

llvm-svn: 101228

current PC.  rdar://7834775

We now produce an identical .o file compared to the cctools
assembler for something like this:

_f0:
L0:
        jmp L1
        .long . - L0
L1:
        jmp A
        .long . - L1

        .zerofill __DATA,_bss,A,0

llvm-svn: 101227

llvm-svn: 101223

llvm-svn: 101214

it can check whether the visible direct callers are passing in parameters to
dead arguments and replace those with undef.

This reinstates r94322 with bugs fixed.

llvm-svn: 101213

llvm-svn: 101210

llvm-svn: 101206

involing getBFCInvMask() where lsb <= msb does not hold true, the disassembler
just returns false, instead of assert, to indicate disassembly error.

llvm-svn: 101205

llvm-svn: 101202

instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder
instance and the client just returns false to indicate disassembly error.

llvm-svn: 101201

llvm-svn: 101191

This test relies on iSel lowering dbg_declare intrinsic when CodeGen::OptLevel is None. On PPC side, CodeGen::OptLevel stays to default when -O0 is used on the command line.

llvm-svn: 101190

bit (we're not trying to build a shared library yet) and generating
the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary.

llvm-svn: 101188

llvm-svn: 101183

llvm-svn: 101182

such that the entire second half is in memory.  Radar 7855014.

llvm-svn: 101181

NULL.

llvm-svn: 101180

code.  It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis.  If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.

llvm-svn: 101179

llvm-svn: 101177

instead of 7, because we are only looking for even rotate amount.

llvm-svn: 101172

llvm-svn: 101171

llvm-svn: 101170

Expand postra machine licm's capability a little more. If an instruction's register operands are all loop invariants, then it's safe to hoist it.

llvm-svn: 101167

Sometimes it is desirable to sink instructions along a critical edge:

x = ...
if (a && b) ...
else use(x);

The 'a && b' condition creates a critical edge to the else block, but we still
want to sink the computation of x into the block. The else block is dominated by
the parent block, so we are not pushing instructions into new code paths.

llvm-svn: 101165

llvm-svn: 101163

Re-apply 101075 and fix it properly. Just reuse the debug info of the branch instruction being optimized. There is no need to --I which can deref off start of the BB.

llvm-svn: 101162