"lane" operand modifier.

llvm-svn: 115843

pseudo instructions.

llvm-svn: 115840

llvm-svn: 115831

llvm-svn: 115798

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

  let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)

llvm-svn: 115720

llvm-svn: 115717

32-bit fp reg, not 64-bit.

Fixes SingleSource.

llvm-svn: 115711

addressing mode from four to five.

llvm-svn: 115645

llvm-svn: 115594

llvm-svn: 115593

so and also change X86 for consistency.

Investigating if this can be improved a bit.

llvm-svn: 115469

1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
   dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.

llvm-svn: 115457

llvm-svn: 115390

llvm-svn: 115376

llvm-svn: 115375

llvm-svn: 115373

llvm-svn: 115370

llvm-svn: 115365

Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs.  For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.

llvm-svn: 115364

been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.

llvm-svn: 115360

llvm-svn: 115354

llvm-svn: 115353

llvm-svn: 115350

llvm-svn: 115344

llvm-svn: 115342

Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.

llvm-svn: 115341

llvm-svn: 115339

Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.

llvm-svn: 115332

llvm-svn: 115314

SingleSource/Regression/C/casts.c.

llvm-svn: 115246

conversion heuristics to the old-style ones.

llvm-svn: 115239

llvm-svn: 115225

llvm-svn: 115203

llvm-svn: 115193

vs. ELF

llvm-svn: 115180

llvm-svn: 115176

llvm-svn: 115160

for the dwarf .loc support to emit dwarf line number tables.

llvm-svn: 115153

llvm-svn: 115149