The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.

A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.

The PointerIntPair class and an internal union are now used, which
reduce the overall size.

llvm-svn: 60806

llvm-svn: 60804

target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!

llvm-svn: 60800

essential problem was that the DAG can contain
random unused nodes which were never analyzed.
When remapping a value of a node being processed,
such a node may become used and need to be analyzed;
however due to operands being transformed during
analysis the node may morph into a different one.
Users of the morphing node need to be updated, and
this wasn't happening.  While there I added a bunch
of documentation and sanity checks, so I (or some
other poor soul) won't have to scratch their head
over this stuff so long trying to remember how it
was all supposed to work next time some obscure
problem pops up!  The extra sanity checking exposed
a few places where invariants weren't being preserved,
so those are fixed too.  Since some of the sanity
checking is expensive, I added a flag to turn it
on.  It is also turned on when building with
ENABLE_EXPENSIVE_CHECKS=1.

llvm-svn: 60797

llvm-svn: 60771

llvm-svn: 60769

one of its operand.

llvm-svn: 60749

Fix the shift amount when unrolling a vector shift into scalar shifts.
Fix problem in getShuffleScalarElt where it assumes that the input of
a bit convert must be a vector.

llvm-svn: 60740

pipeline model.

llvm-svn: 60733

llvm-svn: 60707

and use it in x86 address mode folding. Also, make
getRegForValue return 0 for illegal types even if it has a
ValueMap for them, because Argument values are put in the
ValueMap. This fixes PR3181.

llvm-svn: 60696

llvm-svn: 60684

llvm-svn: 60683

live interval updating.

llvm-svn: 60652

Reason #3 from 60595 doesn't hold true. If we can fold a PIC load from constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing.

llvm-svn: 60596

llvm-svn: 60592

llvm-svn: 60586

changing the stack slots on an instruction, to keep them
consistent with the actual memory addresses.

llvm-svn: 60584

While they appear to provide a normal clobbering def, they don't
in the case of the awkward IMPLICIT_DEF+INSERT_SUBREG idiom. It
would be good to change INSERT_SUBREG; until then, this change
allows post-regalloc scheduling to cope in a mildly conservative
way.

llvm-svn: 60583

llvm-svn: 60553

number of bytes for types such as i1 which are not
a multiple of 8 bits in length.

llvm-svn: 60543

llvm-svn: 60525

llvm-svn: 60524

the main thing this covers is spills to distinct spill slots.

llvm-svn: 60517

issues with subreg operands and tied operands.

llvm-svn: 60510

on PseudoSourceValue values. This also fixes a FIXME in
lib/VMCode/AsmWriter.cpp.

llvm-svn: 60507

llvm-svn: 60500

an area where eventually it would be good to use target-dependent
information.

llvm-svn: 60498

examining non-anti-dependence edges.

llvm-svn: 60496

llvm-svn: 60495

parts, and add target-independent code to add/preserve
MachineMemOperands.

llvm-svn: 60488

llvm-svn: 60487

a new node if the node was actually remapped.

llvm-svn: 60482

Print a single parameter .file directive if we have an ELF target.

llvm-svn: 60480

is set but mayLoad is not set. Fix all the problems this turned up.

Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.

llvm-svn: 60459

1. ppcf128 select is expanded to f64 select's.
2. f64 select operand 0 is an i1 truncate, it's promoted to i32 zero_extend.
3. f64 select is updated. It's changed back to a "NewNode" and being re-analyzed.
4. f64 select operands are being processed. Operand 0 is a "NewNode". It's being expunged out of ReplacedValues map.
5. ExpungeNode tries to remap f64 select and notice it's a "NewNode" and assert.
Duncan, please take a look. Thanks.

llvm-svn: 60443

consistent with the way it's generally done in other places.

llvm-svn: 60439

llvm-svn: 60434

llvm-svn: 60433

llvm-svn: 60432