llvm-svn: 40791

Add a test case to validate code gen for typeof/builtin_types_compatible.

This test case currently generates the following unexpected warnings (when compared with gcc).

[dylan:clang/test/Parser] admin% ../../../../Debug/bin/clang -parse-ast-check builtin_types_compatible.c
Warnings seen but not expected:
  Line 28: expression result unused
  Line 29: expression result unused
  Line 30: expression result unused
  Line 31: expression result unused
  Line 32: expression result unused
  Line 33: expression result unused

llvm-svn: 40789

llvm-svn: 40788

llvm-svn: 40787

Rename AddrLabel and OCUVectorComponent -> AddrLabelExpr and OCUVectorElementExpr respectively.  This is for consistency with other expr nodes end with *Expr.

llvm-svn: 40785

llvm-svn: 40783

   vec2.yx = vec2; // reverse
 

llvm-svn: 40782

    vec2.x = f;

llvm-svn: 40781

llvm-svn: 40780

llvm vector shuffle instead of a bunch of insert/extract operations.
For:   vec4 = vec4.yyyy;  // splat

Emit:
        %tmp1 = shufflevector <4 x float> %tmp, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > 

instead of:

        %tmp1 = extractelement <4 x float> %tmp, i32 1          
        %tmp2 = insertelement <4 x float> undef, float %tmp1, i32 0             
        %tmp3 = extractelement <4 x float> %tmp, i32 1          
        %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1             
        %tmp5 = extractelement <4 x float> %tmp, i32 1          
        %tmp6 = insertelement <4 x float> %tmp4, float %tmp5, i32 2             
        %tmp7 = extractelement <4 x float> %tmp, i32 1          
        %tmp8 = insertelement <4 x float> %tmp6, float %tmp7, i32 3             

llvm-svn: 40779

llvm-svn: 40778

llvm-svn: 40777

llvm-svn: 40776

llvm-svn: 40775

llvm-svn: 40774

llvm-svn: 40772

like this:

typedef __attribute__(( ocu_vector_type(4) )) float float4;
float4 test1(float4 V) {
  return V.wzyx+V;
}

to:
_test1:
        pshufd  $27, %xmm0, %xmm1
        addps   %xmm0, %xmm1
        movaps  %xmm1, %xmm0
        ret

and:

_test1:
        mfspr r2, 256
        oris r3, r2, 4096
        mtspr 256, r3
        li r3, lo16(LCPI1_0)
        lis r4, ha16(LCPI1_0)
        lvx v3, r4, r3
        vperm v3, v2, v2, v3
        vaddfp v2, v3, v2
        mtspr 256, r2
        blr 

llvm-svn: 40771

We can now codegen:

  vec4.xy;

as nothing!

llvm-svn: 40769

llvm-svn: 40768

llvm-svn: 40766

llvm-svn: 40765

llvm-svn: 40764

llvm-svn: 40763

llvm-svn: 40762

llvm-svn: 40761

llvm-svn: 40760

llvm-svn: 40759

llvm-svn: 40758

llvm-svn: 40757

Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756

llvm-svn: 40754

llvm-svn: 40751

llvm-svn: 40750

llvm-svn: 40749

llvm-svn: 40748

llvm-svn: 40746

llvm-svn: 40745

llvm-svn: 40743

casts in the input.

llvm-svn: 40741

llvm-svn: 40740