llvm-svn: 45638

checking that there was a from a global instead of a load from the stub
for a global, which is the one that's safe to hoist.

Consider this program:

volatile char G[100];
int B(char *F, int N) {
  for (; N > 0; --N)
    F[N] = G[N];
}

In static mode, we shouldn't be hoisting the load from G:

$ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm

LBB1_1: # bb.preheader
        leal    -1(%eax), %edx
        testl   %edx, %edx
        movl    $1, %edx
        cmovns  %eax, %edx
        xorl    %esi, %esi
LBB1_2: # bb
        movb    _G(%eax), %bl
        movb    %bl, (%ecx,%eax)

llvm-svn: 45626

for remat, but can't due to an RA bug.

llvm-svn: 45623

llvm-svn: 45622

llvm-svn: 45621

isReallySideEffectFree and isReallyTriviallyReMaterializable.  Why is a load from
a global considered side-effect-free but not rematable?

llvm-svn: 45620

llvm-svn: 45603

check that register isn't 0 before going further.

llvm-svn: 45498

llvm-svn: 45484

Fix a bug in my previous patch: refer to the impl not the pure virtual version.  It's unclear why gcc would ever compile this...

llvm-svn: 45476

a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475

Machine-level API cleanup instigated by Chris.

llvm-svn: 45470

that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467

e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464

Use MachineOperand::getImm instead of MachineOperand::getImmedValue.  Likewise setImmedValue -> setImm

llvm-svn: 45453

function, then go ahead and hoist it out of the loop. This is the result:

$ cat a.c
volatile int G;

int A(int N) {
  for (; N > 0; --N)
    G++;
}
$ llc -o - -relocation-model=pic
_A:
...
LBB1_2: # bb
        movl    L_G$non_lazy_ptr-"L1$pb"(%eax), %esi
        incl    (%esi)
        incl    %edx
        cmpl    %ecx, %edx
        jne     LBB1_2  # bb
...
$ llc -o - -relocation-model=pic -machine-licm
_A:
...
        movl    L_G$non_lazy_ptr-"L1$pb"(%eax), %eax
LBB1_2: # bb
        incl    (%eax)
        incl    %edx
        cmpl    %ecx, %edx
        jne     LBB1_2  # bb
...

I'm limiting this to the MOV32rm x86 instruction for now.

llvm-svn: 45444

llvm-svn: 45418

based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.

llvm-svn: 45132

llvm-svn: 44727

  isTriviallyReMaterializable -> hasNoSideEffects
  isReallyTriviallyReMaterializable -> isTriviallyReMaterializable

llvm-svn: 44702

enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870

llvm-svn: 42783

llvm-svn: 42761

to its inverse.
Testing this as llcbeta

llvm-svn: 42661

llvm-svn: 42655

cause performance degradation.

llvm-svn: 42653

leal 1(%ecx), %edi, which requires 67H prefix.

llvm-svn: 42647

llvm-svn: 42642

llvm-svn: 42630

llvm-svn: 42459

Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.

llvm-svn: 42285

can terminate a block with no fall-through.

llvm-svn: 42029

llvm-svn: 41975

llvm-svn: 41962

Patch by Sterling Stein!

llvm-svn: 41758

leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx

llvm-svn: 41735

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

llvm-svn: 40537

llvm-svn: 37960

their names are changed.

llvm-svn: 37876