Commits · 2d9bb65b3dee3d84a523f043b6059bce2a4a1032 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Aug 22, 2014
- ARM / x86_64 varargs: Don't save regparms in prologue without va_start · 2d9bb65b
  Reid Kleckner authored Aug 22, 2014
  2d9bb65b
- R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment · f3fc555e
  Tom Stellard authored Aug 22, 2014
  f3fc555e
- R600/SI: Use a ComplexPattern for DS loads and stores · 85e8b6d5
  Tom Stellard authored Aug 22, 2014
  85e8b6d5
- R600/SI: Wrap local memory pointer in AssertZExt on SI · ca7ecf3d
  Tom Stellard authored Aug 22, 2014
  ca7ecf3d
- R600/SI: Use correct helper class for DS_WRITE2 instructions · 0510514e
  Tom Stellard authored Aug 22, 2014
  0510514e
- [ARM] Move the implementation of the target hooks related to copy-related · d358e84d
  Quentin Colombet authored Aug 22, 2014
  d358e84d
- [mips] Don't use odd-numbered float registers for double arguments for fastcc · 86ebfe24
  Sasa Stankovic authored Aug 22, 2014
  86ebfe24
- Revert "X86: Align the stack on word boundaries in LowerFormalArguments()" · c667974b
  Duncan P. N. Exon Smith authored Aug 21, 2014
  c667974b
- [FastISel][AArch64] Add support for variable shift. · 0e0b4c1c
  Juergen Ributzka authored Aug 21, 2014
  0e0b4c1c
- Minor refactor to make applying patches from 'Add a "probe-stack" attribute'... · 2c52c668
  Philip Reames authored Aug 21, 2014
  2c52c668
- name change: isPow2DivCheap -> isPow2SDivCheap · 2cdea4c4
  Sanjay Patel authored Aug 21, 2014
  2cdea4c4
- Whitespace change to reduce diff in future patch. · 4e8cb794
  Philip Reames authored Aug 21, 2014
  4e8cb794
- [X86] Split out the logic to select the stack probe function (NFC) · 34fcca72
  Philip Reames authored Aug 21, 2014
  34fcca72
Aug 21, 2014
- Rename AtomicExpandLoadLinked into AtomicExpand · 59c23cd9
  Robin Morisset authored Aug 21, 2014
  59c23cd9
- [FastISel][AArch64] Use the correct register class to make the MI verifier happy. · addb75a4
  Juergen Ributzka authored Aug 21, 2014
  addb75a4
- R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructions · 745f2edd
  Tom Stellard authored Aug 21, 2014
  745f2edd
- R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as Live-In to the function · 162a9471
  Tom Stellard authored Aug 21, 2014
  162a9471
- R600/SI: Remove unused SGPR spilling code · 8e52375b
  Tom Stellard authored Aug 21, 2014
  8e52375b
- R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudos · c5cf2f04
  Tom Stellard authored Aug 21, 2014
  c5cf2f04
- R600/SI: Handle VCC in SIRegisterInfo::getPhysRegSubReg() · 11aa80cc
  Tom Stellard authored Aug 21, 2014
  11aa80cc
- [AVX512] Add class to group common template arguments related to vector type · 5ed17dad
  Adam Nemet authored Aug 21, 2014
  5ed17dad
- [AArch64] Run a peephole pass right after AdvSIMD pass. · 0c740d4b
  Quentin Colombet authored Aug 21, 2014
  0c740d4b
- [FastISel][AArch64] Factor out ANDWri instruction generation into a helper function. NFCI. · c83265a6
  Juergen Ributzka authored Aug 21, 2014
  c83265a6
- Thumb1 load/store optimizer: Improve code to materialize new base register. · dfdda0d4
  Moritz Roth authored Aug 21, 2014
  dfdda0d4
- Add a thread-model knob for lowering atomics on baremetal & single threaded systems · 5e98ff96
  Jonathan Roelofs authored Aug 21, 2014
  5e98ff96
- X86AsmPrinter MCJIT MSVC bug fix. · fbe17d6a
  Josh Klontz authored Aug 21, 2014
  fbe17d6a
- [ARM] Enable DP copy, load and store instructions for FPv4-SP · 51b1d460
  Oliver Stannard authored Aug 21, 2014
  51b1d460
- Reassociate x + -0.1234 * y into x - 0.1234 * y · 2b98bd2a
  Erik Verbruggen authored Aug 21, 2014
  2b98bd2a
- X86: Turn redundant if into an assertion. · b791ef21
  Benjamin Kramer authored Aug 21, 2014
  b791ef21
- [x86] Added _addcarry_ and _subborrow_ intrinsics · 46409eae
  Robert Khasanov authored Aug 21, 2014
  46409eae
- [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes · 86ca6aaf
  Robert Khasanov authored Aug 21, 2014
  86ca6aaf
- [x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM. · 7c5a8436
  Robert Khasanov authored Aug 21, 2014
  7c5a8436
- [x86] Enable Broadwell target. · 98441b6e
  Robert Khasanov authored Aug 21, 2014
  98441b6e
- Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid needing to mention the size. · 71b7b68b
  Craig Topper authored Aug 21, 2014
  71b7b68b
- [ARM] Mark VSETLNi32 with the InsertSubreg property and implement the related · 84f15bd1
  Quentin Colombet authored Aug 21, 2014
  84f15bd1
- [LoopVectorize] Up the maximum unroll factor to 4 for AArch64 · a88896b5
  James Molloy authored Aug 21, 2014
  a88896b5
- Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence · 44937d98
  Jonathan Roelofs authored Aug 20, 2014
  44937d98
- [ARM] Mark VMOVRRD with the ExtractSubreg property and implement the related · deb82eab
  Quentin Colombet authored Aug 20, 2014
  deb82eab
Aug 20, 2014
- Fix undefined behavior (left shift of negative value) in SystemZ backend. · fffd56ec
  Alexey Samsonov authored Aug 20, 2014
  fffd56ec
- Fix undefined behavior (left shift of negative value) in Hexagon backend. · 2651ae65
  Alexey Samsonov authored Aug 20, 2014
  2651ae65