llvm-svn: 74693

Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.

llvm-svn: 74692

llvm-svn: 74683

llvm-svn: 74681

llvm-svn: 74658

llvm-svn: 74650

addressing mode is encoded in the second operand, not the third.

llvm-svn: 74641

bytes and not bytes.

llvm-svn: 74624

Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.

llvm-svn: 74580

 - This more or less amounts to a revert of r65379. I'm curious to know what
   happened that caused this variable to become unused.

llvm-svn: 74579

llvm-svn: 74577

llvm-svn: 74566

have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.

This allows for future work that would allow for precise no-op placement and the
like.

llvm-svn: 74564

llvm-svn: 74555

llvm-svn: 74549

llvm-svn: 74543

llvm-svn: 74500

llvm-svn: 74468

Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.

llvm-svn: 74423

to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.

llvm-svn: 74421

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

llvm-svn: 74385

llvm-svn: 74384

llvm-svn: 74382

llvm-svn: 74368

llvm-svn: 74357

When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.

llvm-svn: 74355

Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329

llvm-svn: 74322

llvm-svn: 74321

llvm-svn: 74293

Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288

llvm-svn: 74277

llvm-svn: 74255

llvm-svn: 74241

llvm-svn: 74239

llvm-svn: 74237

llvm-svn: 74236

llvm-svn: 74228

llvm-svn: 74223