operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944

llvm-svn: 11943

to run the die pass after it.

llvm-svn: 11942

Create a new AddUsesToWorkList method
optimize memmove/set/cpy of zero bytes to a noop.

llvm-svn: 11941

llvm-svn: 11940

llvm-svn: 11939

llvm-svn: 11938

llvm-svn: 11937

function, as long as the loop isn't the only one in that function. This should
help debugging passes easier with BugPoint.

llvm-svn: 11936

a new function, taking care of inputs and outputs.

llvm-svn: 11935

llvm-svn: 11934

llvm-svn: 11933

llvm-svn: 11932

an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931

llvm-svn: 11930

llvm-svn: 11929

llvm-svn: 11928

llvm-svn: 11927

instructions.

llvm-svn: 11923

them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922

llvm-svn: 11921

llvm-svn: 11919

llvm-svn: 11915

llvm-svn: 11913

llvm-svn: 11912

llvm-svn: 11911

llvm-svn: 11908

instructions.

llvm-svn: 11907

each MachineOperand. We don't really need an int64_t immediate :-).

llvm-svn: 11906

llvm-svn: 11905

llvm-svn: 11903

consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902

llvm-svn: 11901

This is a really minor thing, but might help out the 'switch statement induction'
code in simplifycfg.

llvm-svn: 11900

llvm-svn: 11899

llvm-svn: 11898

llvm-svn: 11896

that they are as far away from the loads as possible.

llvm-svn: 11895

MRegisterInfo::isPhysicalRegister().

llvm-svn: 11894

llvm-svn: 11892