llvm-svn: 186930

llvm-svn: 186929

llvm-svn: 186928

llvm-svn: 186924

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186923

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186922

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186921

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186920

This increases the number of opportunites we have for folding.  With the
previous implementation we were unable to fold into any instructions
other than the first when multiple instructions were selected from a
single SDNode.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186919

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186918

Before:

MOV * T0.W, KC0[131-128].Y

After:

MOV * T0.W, KC0[3].Y

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186917

A side-effect of this is that now the compiler expects kernel arguments
to be 4-byte aligned.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186916

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186915

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186914

llvm-svn: 186913

llvm-svn: 186910

llvm-svn: 186907

This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency.

llvm-svn: 186904

MDNodes used by DbgDeclareInst and DbgValueInst.

Another 16 testing cases failed and they are disabled with
-disable-debug-info-verifier.
A total of 34 cases are disabled with -disable-debug-info-verifier and will be
corrected.

llvm-svn: 186902

It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied.

llvm-svn: 186900

Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form.

llvm-svn: 186897

llvm-svn: 186896

llvm-svn: 186893

llvm-svn: 186892

llvm-svn: 186890

llvm-svn: 186887

llvm-svn: 186886

llvm-svn: 186885

When we vectorize across multiple basic blocks we may vectorize PHINodes that create a cycle. We already break the cycle on phi-nodes, but arithmetic operations are still uplicated. This patch adds code that checks if the operation that we are vectorizing was vectorized during the visit of the operands and uses this value if it can.

llvm-svn: 186883

llvm-svn: 186880

llvm-svn: 186879

absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878

llvm-svn: 186877

llvm-svn: 186876

[stackprotector] Changed isNoopBitcast/sameNoopInput to take TargetLoweringBase instead of TargetLowering.

Both functions only use functionality from TargetLoweringBase.

rdar://13935163

llvm-svn: 186874

Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.

llvm-svn: 186869

No functionality change.

rdar://13935163

llvm-svn: 186868

Instead of just adding the scope to the list, we actually handle the scope.

llvm-svn: 186867

 Use the function attributes to pass along the stack protector buffer size.

 Now that we have robust function attributes, don't use a command line option to
 specify the stack protecto buffer size.

llvm-svn: 186863

Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861