- Oct 08, 2013
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Venkatraman Govindaraju authored
No new testcases. However, this patch makes all supported JIT testcases in test/ExecutionEngine pass on Sparc. llvm-svn: 192176
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Craig Topper authored
Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building. llvm-svn: 192175
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Craig Topper authored
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
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Venkatraman Govindaraju authored
[Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead. llvm-svn: 192160
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- Oct 07, 2013
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Reed Kotler authored
llvm-svn: 192130
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Manman Ren authored
from struct byval to registers. We used to pass 0 which means the alignment of PtrVT. Even when the alignment of the struct is smaller than 4, the LOADs would have alignment of 4, and further optimizations could combine the LOADs into a ldm, which would cause crash. The fix is to pass the alignment of the struct byval. rdar://problem/15144402 llvm-svn: 192126
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Akira Hatanaka authored
llvm-svn: 192125
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Akira Hatanaka authored
llvm-svn: 192124
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Benjamin Kramer authored
Fixes PR17495, where an i24 triggered this code. It's intended to optimize i64 loads on 32 bit x86. llvm-svn: 192123
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Akira Hatanaka authored
llvm-svn: 192122
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Akira Hatanaka authored
accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. llvm-svn: 192119
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Amara Emerson authored
llvm-svn: 192111
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Chad Rosier authored
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. llvm-svn: 192107
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Rafael Espindola authored
They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
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Tim Northover authored
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
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Craig Topper authored
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. llvm-svn: 192090
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Craig Topper authored
llvm-svn: 192089
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Craig Topper authored
Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. llvm-svn: 192088
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Craig Topper authored
llvm-svn: 192086
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- Oct 06, 2013
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Benjamin Kramer authored
Regalloc can emit unaligned spills nowadays, but we can't fold the spills into SSE ops if we can't guarantee alignment. PR12250. llvm-svn: 192064
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Elena Demikhovsky authored
Fixed load folding in VPERM2I instruction. llvm-svn: 192063
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Venkatraman Govindaraju authored
llvm-svn: 192056
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Elena Demikhovsky authored
in case of BLEND and added VSHUFPS patterns. llvm-svn: 192055
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Venkatraman Govindaraju authored
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes. llvm-svn: 192054
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Venkatraman Govindaraju authored
addx/subx does not modify conditional codes whereas addxcc/subxx does. llvm-svn: 192053
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- Oct 05, 2013
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Craig Topper authored
llvm-svn: 192046
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Nick Lewycky authored
are directly tied to the flag names in clang with no remapping in between? llvm-svn: 192044
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Craig Topper authored
llvm-svn: 192040
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Craig Topper authored
llvm-svn: 192039
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Craig Topper authored
llvm-svn: 192037
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Rafael Espindola authored
When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
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Jiangning Liu authored
llvm-svn: 192028
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Venkatraman Govindaraju authored
llvm-svn: 192023
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Venkatraman Govindaraju authored
llvm-svn: 192015
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Venkatraman Govindaraju authored
llvm-svn: 192006
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Jack Carter authored
llvm-svn: 191993
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Jack Carter authored
llvm-svn: 191992
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Reed Kotler authored
llvm-svn: 191986
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- Oct 04, 2013
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Jack Carter authored
This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file directive processing. Mips assembly requires processing inline directives that directly and indirectly affect the output ELF header flags. This patch handles one ".abicalls". To process these directives we are following the model the code generator uses by storing state in a container as we go through processing and when we detect the end of input file processing, AsmParser is notified and we update the ELF header flags through a MipsELFStreamer method with a call from MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer). This patch will allow other targets the same functionality. Jack llvm-svn: 191982
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Akira Hatanaka authored
instructions in delay slots along with the original branch instructions. llvm-svn: 191978
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