- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).

llvm-svn: 120917

may determine that they cannot be used uninitialized. But that might be a bit
too much for the compiler to determine.

llvm-svn: 120916

llvm-svn: 120913

llvm-svn: 120912

llvm-svn: 120911

llvm-svn: 120910

llvm-svn: 120909

Total size of bin\Release on disk goes from 82.9 MB to 74.2 MB. (~10% saving)

llvm-svn: 120908

llvm-svn: 120907

Total size of bin\Release on disk goes from 83.6 MB to 81.8MB. (~2% saving)

llvm-svn: 120901

Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

llvm-svn: 120892

llvm-svn: 120891

foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

llvm-svn: 120889

llvm-svn: 120888

llvm-svn: 120870

llvm-svn: 120869

llvm-svn: 120868

llvm-svn: 120867

doing that if the target is darwin10 or newer.

This fixes
*) Direct object emission was producing objects without the workaround on
   darwin9.
*) Assembly printing was producing objects with the workaround on linux.

llvm-svn: 120866

llvm-svn: 120865

llvm-svn: 120860

tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

llvm-svn: 120858

llvm-svn: 120857

llvm-svn: 120856

darwin9 linker, what is needed to avoid it and where to get more information.

Also make the workaround simpler. Just the regular end_sequence we normally
create is more than 4 bytes.

Tested by building cctools and ld64 from darwin9 on a darwin10 system and using
those. I checked that I was able to reproduce the bootstrap failure when
the the workaround was disabled.

llvm-svn: 120854

llvm-svn: 120853

operand encoding ordering of the instruction.

llvm-svn: 120852

ARM instruction). Add encoding of bits 13 and 11.

llvm-svn: 120849

halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848

I'm unclear if the tests are actually correct or not, but reverting for now.

llvm-svn: 120847

llvm-svn: 120846

be emitted.

llvm-svn: 120845

llvm-svn: 120844

it completely breaks scalar fp in xmm regs when AVX is enabled.

llvm-svn: 120843

llvm-svn: 120842

llvm-svn: 120841

32-bit wide version by adding the .w suffix.

llvm-svn: 120838

llvm-svn: 120836

immediate offset.

llvm-svn: 120833

llvm-svn: 120832