llvm-svn: 11442

llvm-svn: 11441

llvm-svn: 11433

llvm-svn: 11430

code that worked around problems in the mangler

llvm-svn: 11426

llvm-svn: 11420

llvm-svn: 11417

llvm-svn: 11415

llvm-svn: 11393

llvm-svn: 11375

generating the llvm.memcpy intrinsic.

llvm-svn: 11351

without getting an assertion from ilist that we are dereferencing
ilist<T>::end().

llvm-svn: 11345

llvm-svn: 11342

ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340

llvm-svn: 11335

llvm-svn: 11332

llvm-svn: 11322

llvm-svn: 11317

MO_VirtualRegister but if the register number is one of a physical
register is it considered as a physical register.

llvm-svn: 11315

MO_VirtualRegister but actually be representing a physical register.

llvm-svn: 11310

llvm-svn: 11304

llvm-svn: 11285

llvm-svn: 11282

llvm-svn: 11281

llvm-svn: 11280

llvm-svn: 11277

llvm-svn: 11276

llvm-svn: 11274

I will observe that the concept of using WriteAsOperand is completely broken,
but then we all knew that, didn't we?

llvm-svn: 11255

llvm-svn: 11252

placed into any alignment situation.

llvm-svn: 11247

llvm-svn: 11228

llvm-svn: 11218

operand of the instruction and thus simplify the register allocation.

llvm-svn: 11124

at Chris's request.

llvm-svn: 11120

to be the same (IOW they are not two address instructions).

llvm-svn: 11117

llvm-svn: 11098

llvm-svn: 11095

llvm-svn: 11094

llvm-svn: 11081