llvm-svn: 118389

llvm-svn: 118375

the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.

I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.

llvm-svn: 118363

to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.

llvm-svn: 118360

- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.

llvm-svn: 118357

(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.

llvm-svn: 118351

llvm-svn: 118341

llvm-svn: 118340

llvm-svn: 118339

while the latter doesn't.

llvm-svn: 118338

Fixes 8559.

llvm-svn: 118333

llvm-svn: 118310

llvm-svn: 118307

llvm-svn: 118304

llvm-svn: 118301

llvm-svn: 118300

llvm-svn: 118295

llvm-svn: 118291

(relocations, e.g.), but this will allow simple things to flow through.

llvm-svn: 118289

llvm-svn: 118288

llvm-svn: 118280

and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245

Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.

llvm-svn: 118237

tweaking when we start using it for object file emission or JIT, but it's a
start.

llvm-svn: 118221

llvm-svn: 118220

CodeEmitter.

llvm-svn: 118209

This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204

We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201

llvm-svn: 118199

llvm-svn: 118192

all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183

llvm-svn: 118176

For NEON we had been assuming this was always an immediate constant.

llvm-svn: 118175

with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169

value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167

Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.

llvm-svn: 118160

llvm-svn: 118152

llvm-svn: 118151

easier to read.

llvm-svn: 118148

    vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144