- Feb 22, 2006
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Jim Laskey authored
llvm-svn: 26314
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Evan Cheng authored
Fixed some existing bugs (wrong predicates, prefixes) at the same time. llvm-svn: 26310
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Chris Lattner authored
llvm-svn: 26308
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Chris Lattner authored
llvm-svn: 26305
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- Feb 21, 2006
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Evan Cheng authored
llvm-svn: 26303
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Evan Cheng authored
llvm-svn: 26302
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Evan Cheng authored
llvm-svn: 26301
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Evan Cheng authored
llvm-svn: 26300
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Chris Lattner authored
llvm-svn: 26299
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Chris Lattner authored
instructions are expensive. llvm-svn: 26298
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Evan Cheng authored
llvm-svn: 26297
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Evan Cheng authored
llvm-svn: 26296
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Evan Cheng authored
Added generic vector types: VR64 and VR128. llvm-svn: 26295
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- Feb 20, 2006
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Evan Cheng authored
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). llvm-svn: 26294
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Evan Cheng authored
llvm-svn: 26292
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- Feb 18, 2006
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Evan Cheng authored
advantage of fisttpll. llvm-svn: 26288
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Nate Begeman authored
that the shift may be more easily folded into other operations. llvm-svn: 26286
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Evan Cheng authored
llvm-svn: 26283
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Evan Cheng authored
llvm-svn: 26281
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Evan Cheng authored
llvm-svn: 26278
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Evan Cheng authored
llvm-svn: 26273
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Evan Cheng authored
llvm-svn: 26272
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- Feb 17, 2006
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Chris Lattner authored
llvm-svn: 26260
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Evan Cheng authored
llvm-svn: 26259
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Nate Begeman authored
and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. llvm-svn: 26255
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Chris Lattner authored
llvm-svn: 26253
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Jeff Cohen authored
llvm-svn: 26252
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Nate Begeman authored
llvm-svn: 26250
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Nate Begeman authored
llvm-svn: 26249
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Evan Cheng authored
issue. Need to do more experiments. llvm-svn: 26247
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Nate Begeman authored
llvm-svn: 26246
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Evan Cheng authored
llvm-svn: 26245
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Evan Cheng authored
llvm-svn: 26244
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Chris Lattner authored
other small targets that do that can be learned from. They also have the added advantage of being tested :) llvm-svn: 26243
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- Feb 16, 2006
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Evan Cheng authored
proves to be worth 20% on Ptrdist/ks. Might be related to dependency breaking support. 2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These are used for FR32 / FR64 reg-to-reg copies. 3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to spill / restore FsMOVAPSrr and FsMOVAPDrr. llvm-svn: 26241
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Evan Cheng authored
llvm-svn: 26240
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Nate Begeman authored
and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
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Evan Cheng authored
llvm-svn: 26234
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Duraid Madina authored
distinguish between objects and register names, now we can have stuff with names like "f84", "in6" etc etc. this should fix one or two tests llvm-svn: 26232
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Evan Cheng authored
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. llvm-svn: 26231
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