llvm-svn: 141853

The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819

llvm-svn: 141811

llvm-svn: 141794

llvm-svn: 141786

llvm-svn: 141781

llvm-svn: 141780

llvm-svn: 141761

Remove unused classes.

llvm-svn: 141757

llvm-svn: 141749

When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

llvm-svn: 141746

llvm-svn: 141743

instructions with two register operands derive from it.

llvm-svn: 141742

llvm-svn: 141737

arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736

llvm-svn: 141722

Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721

llvm-svn: 141720

the real instructions.

llvm-svn: 141718

llvm-svn: 141716

llvm-svn: 141715

llvm-svn: 141708

We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

llvm-svn: 141704

llvm-svn: 141696

llvm-svn: 141695

llvm-svn: 141694

llvm-svn: 141682

llvm-svn: 141671

This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).

llvm-svn: 141666

llvm-svn: 141665

llvm-svn: 141656

llvm-svn: 141654

llvm-svn: 141651

Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.

llvm-svn: 141642

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

The VMOVS widening needs to look at the implicit COPY operands.  Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.

The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.

llvm-svn: 141619

Mips64.

llvm-svn: 141618

llvm-svn: 141616

llvm-svn: 141615

llvm-svn: 141613