llvm-svn: 150606

This reverts commit 1656806a944bbd23e98c6e578810fe02495ab741.

llvm-svn: 150605

as it's breaking the build.

This reverts commit 11241abca5e2a313412fed594bb9d9fa2a2057fb.

llvm-svn: 150604

llvm-svn: 150603

llvm-svn: 150601

llvm-svn: 150591

The c'tor list is stored as a list of 'void ()*'s, so all of the functions are
bitcast to that. However, the dyn_cast doesn't automagically look through
bitcasts. Do that for it.
<rdar://problem/10813350>

llvm-svn: 150572

Added TargetPassConfig::disablePass/substitutePass as a general mechanism to override specific passes.

llvm-svn: 150562

llvm-svn: 150538

Stop custom lowering forr x86 DEC64m from happening if the load in the lowered sequence has more than 1 user

llvm-svn: 150537

llvm-svn: 150536

llvm-svn: 150520

Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel.

llvm-svn: 150462

llvm-svn: 150447

llvm-svn: 150444

marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.

llvm-svn: 150437

llvm-svn: 150433

llvm-svn: 150365

- Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default.
- Remove misplaced llvm_unreachable.
- Add static to a declaration of a function on MSVC x86 only.
- Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable.

llvm-svn: 150364

Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel.

llvm-svn: 150363

llvm-svn: 150362

Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.

llvm-svn: 150360

It caused 3 failures on pre-penryn and non-x86(generic) hosts.

llvm-svn: 150357

If the DEC node had more than one user, it was doing this lowering but
leaving the original DEC node around and so decrementing twice.

Fixes PR11964.

llvm-svn: 150356

llvm-svn: 150328

to TargetLibraryInfo and use one of them in GlobalOpt.

llvm-svn: 150323

llvm-svn: 150321

llvm-svn: 150314

Patch by Kai Nacke!

llvm-svn: 150307

llvm-svn: 150305

llvm-svn: 150304

This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

llvm-svn: 150303

Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel.

llvm-svn: 150299

Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel.

llvm-svn: 150296

Now that the clang driver passes the CPU and feature information to
the backend when processing assembly files (150273), this isn't necessary.

llvm-svn: 150274

llvm-svn: 150251

llvm-svn: 150228

llvm-svn: 150227

Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

llvm-svn: 150226

rdar://10838899

llvm-svn: 150222