When the scalar compare is between floating point and operands are
vector, we custom lower SELECT_CC to use NEON SIMD compare for
generating less instructions.

llvm-svn: 200365

Oops. Don't do build tests on patches like that with --enable-targets=x86_64

llvm-svn: 200355

The subtarget info is explicitly passed to the EncodeInstruction
method and we should use that subtarget info to influence any
encoding decisions.

llvm-svn: 200350

llvm-svn: 200349

llvm-svn: 200348

llvm-svn: 200345

As opposed to GCC/GAS the default ABI for Mips64 is n64.
Compatibility bit should be set if o32 ABI is used when targeting Mips64.

llvm-svn: 200332

The code was missing the case for aggregate parameters and
hence was emitting them as .b0 type. Also fixed a couple
of comments.

llvm-svn: 200325

This improves the fix committed at revision 199683 adding the
following new target specific combine rules:

1) fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
        (v4i32 (bitcast (movsd (v2i64 (bitcast A)), (v2i64 (bitcast B))) ))

2) fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
        (v4f32 (bitcast (movsd (v2f64 (bitcast A)), (v2f64 (bitcast B))) ))

3) fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
        (v4i32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))

4) fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
        (v4f32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) ))

llvm-svn: 200324

At present, this handles .tc (error) and needs to be expanded to deal properly with .machine

llvm-svn: 200309

GPRC_NOR0 is not a subclass of GPRC (because it also contains the ZERO pseudo
register). As a result, we also need to check for it in the spilling code.

llvm-svn: 200288

Fixes half a dozen piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200283

Also emit the stubs that were generated for references to typeinfo
symbols.

llvm-svn: 200282

This avoids miscompiling MS inline asm in LLVM where we have to infer
clobbers.  Test case forthcoming in Clang.

llvm-svn: 200279

[TLI] Add a new hook to TargetLowering to query the target if a load of a constant should be converted to simply the constant itself.

Before this patch we used getIntImmCost from TargetTransformInfo to determine if
a load of a constant should be converted to just a constant, but the threshold
for this was set to an arbitrary value. This value works well for the two
targets (X86 and ARM) that implement this target-hook, but it isn't
target-independent at all.

Now targets have the possibility to decide directly if this optimization should
be performed. The default value is set to false to preserve the current
behavior. The target hook has been moved to TargetLowering, which removed the
last use and need of TargetTransformInfo in SelectionDAG.

llvm-svn: 200271

code to see if we're emitting a function into a non-default
text section. This is still a less-than-ideal solution, but more
contained than r199871 to determine whether or not we're emitting
code into an array of comdat sections.

llvm-svn: 200269

This brings MC into line with GNU 'as' on ARM, and it brings the ARM
target into line with most other LLVM targets, which declare the
initial CFI state with addInitialFrameState().

Without this, functions generated with .cfi_startproc/endproc on ARM
will tend to cause GDB to abort with:
  gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule.

I've also tested this by comparing the output of "readelf -w" on the
object files produced by llvm-mc and gas when given the .s file added
here.

This change is part of addressing PR18636.

Differential Revision: http://llvm-reviews.chandlerc.com/D2597

llvm-svn: 200255

Summary:
This commit gives an address mode to the PLD instruction. We
were getting an assertion failure in the frame lowering code
because we had code that was doing a pld of a stack allocated
address. The frame lowering was checking the address mode and
then asserting because pld had none defined.

This commit fixes pld for arm mode. There was a previous fix for
thumb mode in a separate commit. The commit for thumb mode
added a test in a separate file because it would otherwise fail
for arm. This commit moves the thumb test back into the prefetch.ll
file and adds the corresponding arm test.

Differential Revision: http://llvm-reviews.chandlerc.com/D2622

llvm-svn: 200248

llvm-svn: 200244

llvm-svn: 200216

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200196

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200195

Testing this also found the missing '\n' after .frame that this patch also
fixes.

llvm-svn: 200192

llvm-svn: 200186

Replace r199791.

llvm-svn: 200180

It's old version which has some bugs. I'll commit lattest patch soon.

llvm-svn: 200179

llvm-svn: 200178

llvm-svn: 200174

Sorry about that.

llvm-svn: 200171

llvm-svn: 200170

llvm-svn: 200169

llvm-svn: 200167

If a complex expression was passed to the .word directive and the first part of
the directive failed to parse, a secondary diagnostic would be produced that
would clutter the error diagnostics.  Improve the diagnostics by consuming the
remainder of the statement.

llvm-svn: 200160

Fix indentation, remove unnecessary line.  NFC.

llvm-svn: 200158

lib/Target/X86/Disassembler/X86DisassemblerDecoder.c:1361:7: error: C++ style comments are not allowed in ISO C90

llvm-svn: 200153

llvm-svn: 200152

llvm-svn: 200141

These were:
* noreorder handling on the target object streamer and asm parser.
* setting the initial flag bits based on the enabled features.
* setting the elf header flag for micromips

It is *really* depressing I am the one doing this instead of someone at
mips actually taking the time to understand the infrastructure.

llvm-svn: 200138

With this the target streamers will be able to know the target features that
are in use.

llvm-svn: 200135

The popc instruction is defined in the SPARCv9 instruction set
architecture, but it was emulated on CPUs older than Niagara 2.

llvm-svn: 200131