r179494 switched to using the object file info to retrieve the default text
section for some MC streamers. It is possible that initializing an MC
streamer can request sections before the object file info is initialized
when the AutoInitSections flag is set on the streamer.

llvm-svn: 185670

Supports GAS flags "abdnrswxy". No support for alignment or subsections.

Fixes PR16366.

llvm-svn: 185669

This transform was originally added in r185257 but later removed in
r185415.  The original transform would create instructions speculatively
and then discard them if the speculation was proved incorrect.  This has
been replaced with a scheme that splits the transform into two parts:
preflight and fold.  While we preflight, we build up fold actions that
inform the folding stage on how to act.

llvm-svn: 185667

llvm-svn: 185664

llvm-svn: 185663

[PowerPC] Implement writeNopData

This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.

This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.

llvm-svn: 185662

llvm-svn: 185651

This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.

llvm-svn: 185642

[PowerPC] Add all trap mnemonics

This adds support for all basic and extended variants
of the trap instructions to the asm parser.

llvm-svn: 185638

[PowerPC] Add asm parser support for CR expressions

This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".

llvm-svn: 185633

This allows us to create switches even if instcombine has munged two of the
incombing compares into one and some bit twiddling. This was motivated by enum
compares that are common in clang.

llvm-svn: 185632

These exception-related opcodes are not used any longer.

llvm-svn: 185625

llvm-svn: 185620

llvm-svn: 185618

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be  scheduled at the top of the
basic block.

This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.

This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.

A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.

llvm-svn: 185617

Compute the insertion point from the end of the basic block instead of
skipping labels from the front.

This caused failures in landing pads when live-in copies where inserted
before instruction selection.

llvm-svn: 185616

This will soon be tested by exception handling working at all.

llvm-svn: 185615

llvm-svn: 185612

llvm-svn: 185607

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185606

llvm-svn: 185605

llvm-svn: 185603

Patch by pashev.igor.

llvm-svn: 185601

Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600

These exception-related opcodes are not used any longer.

llvm-svn: 185596

Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be  scheduled at the top of the
basic block.

This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.

This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.

A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.

llvm-svn: 185595

This function adds a live-in physical register to an MBB and ensures
that it is copied to a virtual register immediately.

llvm-svn: 185594

Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for the GHC calling convention.

This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening...

llvm-svn: 185592

llvm-svn: 185589

for them and update all uses.

llvm-svn: 185588

In the ARM back-end, build_vector nodes are lowered to a target specific
build_vector that uses floating point type. 
This works well, unless the inserted bitcasts survive until instruction
selection. In that case, they incur moves between integer unit and floating
point unit that may result in inefficient code.

In other words, this conversion may introduce artificial dependencies when the
code leading to the build vector cannot be completed with a floating point type.

In particular, this happens when loads are not aligned.

Before this patch, in that case, the compiler generates general purpose loads
and creates the floating point vector from them, instead of directly using the
vector unit.

The patch uses a vector friendly sequence of code when the inserted bitcasts to
floating point survived DAGCombine.

This is done by a target specific DAGCombine that changes the target specific
build_vector into a sequence of insert_vector_elt that get rid of the bitcasts.

<rdar://problem/14170854>

llvm-svn: 185587

llvm-svn: 185586

(and for consistency).

llvm-svn: 185585

Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous.

llvm-svn: 185583

ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.

Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.

The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.

This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.

Fixes <rdar://problem/14224440>.

llvm-svn: 185575

llvm-svn: 185573

Patch by Alex Crichton <alex@crichton.co>.  Approved by Chris Lattner.

llvm-svn: 185566

[PowerPC] Support lmw/stmw in the asm parser

This adds support for the load/store multiple instructions,
currently used by the asm parser only.

llvm-svn: 185564

[PowerPC] Use mtocrf when available

Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf.  This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible.  It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything.  Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.

llvm-svn: 185561

[PowerPC] Always use mfocrf if available

When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.

Current code makes that distinction in many, but not all places
where a single CR register value is retrieved.  One missing
location is PPCRegisterInfo::lowerCRSpilling.

To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.

On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.

This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.

The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.

Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.

llvm-svn: 185556