Add a spiller option to llc. A simple spiller will come soon. When we get CFG in the machine code represenation a global spiller will also be possible. Also document the linear scan register allocator but mark it as experimental for now.

llvm-svn: 12062

llvm-svn: 12058

* Doxygenify (some) comments

llvm-svn: 12057

llvm-svn: 12055

* Add comments to ExtractLoop()

llvm-svn: 12053

that Instructions are annotable again

llvm-svn: 12045

llvm-svn: 12044

(16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's
dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in
the interest of not breaking things any more than they already are, I'm going
to leave the constant alone.

llvm-svn: 12043

llvm-svn: 12031

Removing old graph files with new graph files that I wrote. Updated ModuloScheduling pass, but still in progress.

llvm-svn: 12030

llvm-svn: 12029

of generating this code:

        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        call Y

we now generate:
        mov DWORD PTR [%ESP], 4
        mov DWORD PTR [%ESP + 4], 123
        call Y

Which hurts the eyes less.  :)

Considering that register pressure around call sites is already high (with all
of the callee clobber registers n stuff), this may help a lot.

llvm-svn: 12028

to function calls, we would emit dead code, like this:

int Y(int, short, double);
int X() {
  Y(4, 123, 4);
}

--- Old
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
***     mov %AX, 123
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Now we emit:
X:
        sub %ESP, 20
        mov %EAX, 4
        mov DWORD PTR [%ESP], %EAX
        mov %AX, 123
        movsx %EAX, %AX
        mov DWORD PTR [%ESP + 4], %EAX
        fld QWORD PTR [.CPIX_0]
        fstp QWORD PTR [%ESP + 8]
        call Y
        mov %EAX, 0
        # IMPLICIT_USE %EAX %ESP
        add %ESP, 20
        ret

Next up, eliminate the mov AX and movsx entirely!

llvm-svn: 12026

llvm-svn: 12021

* Removing extraneous empty space and empty comment lines

llvm-svn: 12014

being annotable

llvm-svn: 12013

... which tickled the lowerinvoke pass because it used the BCE routines.

llvm-svn: 12012

llvm-svn: 12010

llvm-svn: 12009

llvm-svn: 12007

llvm-svn: 12004

llvm-svn: 12003

llvm-svn: 12002

llvm-svn: 12001

llvm-svn: 11998

operand size is correctly specified.

llvm-svn: 11997

1) For 8-bit registers try to use first the ones that are parts of the
   same register (AL then AH). This way we only alias 2 16/32-bit
   registers after allocating 4 8-bit variables.

2) Move EBX as the last register to allocate. This will cause less
   spills to happen since we will have 8-bit registers available up to
   register excaustion (assuming we use the allocation order). It
   would be nice if we could push all of the 8-bit aliased registers
   towards the end but we much prefer to keep callee saved register to
   the end to avoid saving them on entry and exit of the function.

For example this gives a slight reduction of spills with linear scan
on 164.gzip.

Before:

11221 asm-printer           - Number of machine instrs printed
  975 spiller               - Number of loads added
  675 spiller               - Number of stores added
  398 spiller               - Number of register spills

After:

11182 asm-printer           - Number of machine instrs printed
  952 spiller               - Number of loads added
  652 spiller               - Number of stores added
  386 spiller               - Number of register spills

llvm-svn: 11996

their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995

llvm-svn: 11994

Replace uses of addZImm with addImm.

llvm-svn: 11992

block loops.

llvm-svn: 11990

Note that this is a band-aid put over a band-aid.  This just undisables
tail duplication in on very specific case that it seems to work in.

llvm-svn: 11989

llvm-svn: 11987

llvm-svn: 11986

llvm-svn: 11984

llvm-svn: 11983

llvm-svn: 11982

llvm-svn: 11981

llvm-svn: 11979

llvm-svn: 11977