This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location,
and if you include the old one by accident you will trigger this assert.

llvm-svn: 140848

llvm-svn: 140841

immediate.

llvm-svn: 140839

Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834

llvm-svn: 140827

All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826

slot filler.

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140825

llvm-svn: 140824

This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.

llvm-svn: 140823

llvm-svn: 140821

This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816

handle the case where the retain is in a different basic block.
rdar://10210274.

llvm-svn: 140815

objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.

llvm-svn: 140814

llvm-svn: 140810

llvm-svn: 140807

llvm-svn: 140806

Clean up uses of switch instructions so they are not dependent on the operand ordering.  Patch by Stepan Dyatkovskiy.

llvm-svn: 140803

llvm-svn: 140789

llvm-svn: 140787

llvm-svn: 140786

llvm-svn: 140785

llvm-svn: 140784

llvm-svn: 140783

This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

llvm-svn: 140776

llvm-svn: 140774

llvm-svn: 140773

This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

llvm-svn: 140772

llvm-svn: 140769

llvm-svn: 140767

Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.

llvm-svn: 140762

llvm-svn: 140761

llvm-svn: 140758

llvm-svn: 140755

llvm-svn: 140754

llvm-svn: 140753

This doesn't use formated_raw_ostream because it doesn't support the
functionality needed.

llvm-svn: 140751

llvm-svn: 140745

The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.

This also fixes a bug when adding operands after an implicit operand has
been added manually.  The NumImplicitOps count wasn't kept up to date.

MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added.  It is possible to change an MI opcode and add additional
explicit operands.  They will be inserted before any existing implicit
operands.

The only exception is inline asm instructions where operands are never
reordered.  This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.

llvm-svn: 140744

"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741

It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735