Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.

Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.

This should fix PR15840.

llvm-svn: 191165

llvm-svn: 191164

Summary:
LLVM would crash when trying to come up with a relocation type for
assembly like:
movabsq $V@TPOFF, %rax

Instead, we say the relocation type is R_X86_64_TPOFF64.

Fixes PR17274.

Reviewers: dblaikie, nrieck, rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1717

llvm-svn: 191163

No functional change, just makes the error handling a bit more obvious.

llvm-svn: 191162

llvm-svn: 191161

llvm-svn: 191160

Summary:
Parsing cast expressions during error recovery can put us in a bad
state.  Check to see if the token for a simple-type-specifier makes
sense before further parsing.

Fixes PR17255.

Reviewers: rsmith, doug.gregor, CornedBee, eli.friedman

CC: cfe-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1696

llvm-svn: 191159

llvm-svn: 191158

llvm-svn: 191157

Pre-increment loads are microcoded on the A2, and the address increment occurs
only after the load completes. As a result, the latency of the GPR address
update is an additional 2 cycles on top of the load latency.

llvm-svn: 191156

and protocols can be at global scope only.

llvm-svn: 191155

llvm-svn: 191154

llvm-svn: 191153

llvm-svn: 191152

llvm-svn: 191151

an additional conversion (other than a qualification conversion) would be
required after the explicit conversion.

Conversely, do allow explicit conversion functions to be used when initializing
a temporary for a reference binding in direct-list-initialization.

llvm-svn: 191150

this is required to ignore interceptors when called from the module

llvm-svn: 191149

llvm-svn: 191148

llvm-svn: 191147

rather than a post-processing action, so we can support inserting these checks
at stages other than the end of the initialization. No functionality change
intended.

llvm-svn: 191146

iterator, allocator) constructor with the intention of it being
implicitly converted to the allocator type, it is possible for overload
resolution to favour the (iterator, iterator, enable_if) constructor.
Eliminate this possibility by moving the enable_if to one of the
existing arguments and removing the third argument.

llvm-svn: 191145

llvm-svn: 191144

SROA wants to convert any types of equivalent widths but it's not possible to
convert vectors of pointers to an integer scalar with a single cast. As a
workaround we add a bitcast to the corresponding int ptr type first. This type
of cast used to be an edge case but has become common with SLP vectorization.
Fixes PR17271.

llvm-svn: 191143

Apply LWG 2048.  It is amazing to me that this actually works, but the existing tests confirm that it does.  c++1y status page now showing libc++ is complete for c++1y modulo dynarray issues.

llvm-svn: 191142

llvm-svn: 191141

llvm-svn: 191140

Before:
  size = sizeof * a;

After:
  size = sizeof *a;

llvm-svn: 191139

This reverts commit r191130.

llvm-svn: 191138

Copy and paste error in r190935..

llvm-svn: 191137

llvm-svn: 191136

llvm-svn: 191135

Allow binutils .type and .section directives to take the following
forms:
- @<type>
- %<type>
- "<type>"

llvm-svn: 191134

llvm-svn: 191133

see the comment in code

llvm-svn: 191132

In AVX 256bit vectors are valid vectors and therefore the Type Legalizer doesn't
split the VSELECT and SETCC nodes. AVX only supports MIN/MAX on 128bit vectors
and this fix enables vector splitting for this special case in the X86 DAG
Combiner.

This fix is related to PR16695, PR17002, and <rdar://problem/14594431>.

llvm-svn: 191131

The Type Legalizer recognizes that VSELECT needs to be split, because the type
is to wide for the given target. The same does not always apply to SETCC,
because less space is required to encode the result of a comparison. As a result
VSELECT is split and SETCC is unrolled into scalar comparisons.

This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG
Combiner. If a matching pattern is found, then the result mask of SETCC is
promoted to the expected vector mask for the given target. This mask has usually
te same size as the VSELECT return type (except for Intel KNL). Now the type
legalizer will split both VSELECT and SETCC.

This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX
pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.

llvm-svn: 191130

llvm-svn: 191129

This can revert r191087.

llvm-svn: 191128

llvm-svn: 191127

llvm-svn: 191126