llvm-svn: 152176

llvm-svn: 152175

llvm-svn: 152174

llvm-svn: 152173

llvm-svn: 152172

as well as completely defined classes.

This fixes rdar://10956070

llvm-svn: 152171

Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).

llvm-svn: 152162

Register pair, all lanes subscripting.

llvm-svn: 152157

llvm-svn: 152153

Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150

SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap.

This currently assumes that both sets have the same SmallSize to keep the implementation simple,
a limitation that can be lifted if someone cares.

llvm-svn: 152143

llvm-svn: 152136

llvm-svn: 152131

llvm-svn: 152129

llvm-svn: 152127

llvm-svn: 152122

implementation. Patch by Meador Inge

llvm-svn: 152116

When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

llvm-svn: 152095

llvm-svn: 152089

Make it possible for a target to mark FSUB as Expand.  This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.

llvm-svn: 152079

The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076

llvm-svn: 152070

rdar://10988114

llvm-svn: 152068

llvm-svn: 152066

Use the new composite physical registers.

llvm-svn: 152063

llvm-svn: 152061

With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045

Used to allow context sensitive printing of super-register or sub-register
references.

llvm-svn: 152043

Patch by Sean Silva!

llvm-svn: 152042

Specifically, remove the magic number when checking to see if the copy has a 
glue operand and simplify the checking logic.

rdar://10930395

llvm-svn: 152041

In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036

llvm-svn: 152035

llvm-svn: 152034

llvm-svn: 152027

llvm-svn: 152026

This implicitly fixes a nasty bug in the GVN hashing (that thankfully
could only manifest as a performance bug): actually include the opcode
in the hash. The old code started the hash off with the opcode, but then
overwrote it with the type pointer.

Since this is likely to be pretty hot (GVN being already pretty
expensive) I've included a micro-optimization to just not bother with
the varargs hashing if they aren't present. I can't measure any change
in GVN performance due to this, even with a big test case like Duncan's
sqlite one. Everything I see is in the noise floor. That said, this
closes a loop hole for a potential scaling problem due to collisions if
the opcode were the differentiating aspect of the expression.

llvm-svn: 152025

hashing infrastructure. I wonder why we don't just use StringMap here,
and I may revisit the issue if I have time, but for now I'm just trying
to consolidate.

llvm-svn: 152023

llvm-svn: 152016

llvm-svn: 152014

The first def of a virtual register cannot also read the register.
Assert on such bad machine code instead of trying to fix it.
TwoAddressInstructionPass should never create code like that.

llvm-svn: 152010