Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

llvm-svn: 35082

"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

llvm-svn: 35080

  1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

llvm-svn: 35078

llvm-svn: 35072

Patch by Zhou Sheng.

llvm-svn: 35064

Patch by Zhou Sheng.

llvm-svn: 35063

llvm-svn: 35062

  1. Replace getSignedMinValue() with getSignBit() for better code readability.
  2. Replace APIntOps::shl() with operator<<= for convenience.
  3. Make APInt construction more effective.

llvm-svn: 35060

optimization power.

llvm-svn: 35058

User from the list of I users.

llvm-svn: 35051

llvm-svn: 35027

llvm-svn: 35024

do the correctness/performance analysis testing.

llvm-svn: 35023

llvm-svn: 35022

Provide an APIntified version of MaskedValueIsZero. This will (temporarily)
cause a "defined but not used" message from the compiler. It will be used
in the next patch in this series.

Patch by Sheng Zhou.

llvm-svn: 35019

Add a new ComputeMaskedBits function that is APIntified. We'll slowly
convert things over to use this version. When its all done, we'll remove
the existing version.

llvm-svn: 35018

llvm-svn: 35003

llvm-svn: 35001

llvm-svn: 34996

llvm-svn: 34992

llvm-svn: 34984

llvm-svn: 34939

scalarrepl things down to elements, but mem2reg can't promote elements that
are memset/memcpy'd.  Until then, the code is disabled "0 &&".

llvm-svn: 34924

llvm-svn: 34920

define i64 @test(i64 %A, i32 %B) {
        %tmp12 = zext i32 %B to i64             ; <i64> [#uses=1]
        %tmp3 = shl i64 %tmp12, 32              ; <i64> [#uses=1]
        %tmp5 = add i64 %tmp3, %A               ; <i64> [#uses=1]
        %tmp6 = and i64 %tmp5, 123              ; <i64> [#uses=1]
        ret i64 %tmp6
}

into:

define i64 @test(i64 %A, i32 %B) {
        %tmp6 = and i64 %A, 123         ; <i64> [#uses=1]
        ret i64 %tmp6
}

This implements Transforms/InstCombine/add2.ll:test1

llvm-svn: 34919

llvm-svn: 34917

llvm-svn: 34914

llvm-svn: 34904

llvm-svn: 34902

up simplifycfg by 20%

llvm-svn: 34901

would scan the entire loop body, then scan all users of instructions in the
loop, looking for users outside the loop.  Now, since we know that the
loop is in LCSSA form, we know that any users outside the loop will be LCSSA
phi nodes.  Just scan them.

This speeds up indvars significantly.

llvm-svn: 34898

This makes -indvars require and use LCSSA, updating it as appropriate.

llvm-svn: 34896

llvm-svn: 34891

the order that instcombine processed instructions in the testcase.  The end
result is that instcombine finished with:

define i16 @test1(i16 %a) {
        %tmp = zext i16 %a to i32               ; <i32> [#uses=2]
        %tmp21 = lshr i32 %tmp, 8               ; <i32> [#uses=1]
        %tmp5 = shl i32 %tmp, 8         ; <i32> [#uses=1]
        %tmp.upgrd.32 = or i32 %tmp21, %tmp5            ; <i32> [#uses=1]
        %tmp.upgrd.3 = trunc i32 %tmp.upgrd.32 to i16           ; <i16> [#uses=1]
        ret i16 %tmp.upgrd.3
}

which can't get matched as a bswap.

This patch makes instcombine more sophisticated about removing truncating
casts, allowing it to turn this into:

define i16 @test2(i16 %a) {
        %tmp211 = lshr i16 %a, 8
        %tmp52 = shl i16 %a, 8
        %tmp.upgrd.323 = or i16 %tmp211, %tmp52
        ret i16 %tmp.upgrd.323
}

which then matches as bswap.  This fixes bswap.ll and implements
InstCombine/cast2.ll:test[12].  This also implements cast elimination of
add/sub.

llvm-svn: 34870

llvm-svn: 34868

finish without combining something it is capable of.

llvm-svn: 34865

llvm-svn: 34863

Replace expensive getZExtValue() == 0 calls with isZero() calls.

llvm-svn: 34861

llvm-svn: 34860

llvm-svn: 34859