We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.

llvm-svn: 146150

llvm-svn: 146136

Make sure we correctly set LiveRegGens when a call is unscheduled.  <rdar://problem/10460321>.  No testcase because this is very sensitive to scheduling.

llvm-svn: 146087

llvm-svn: 146083

that he isn't using these any more, so just delete them.

llvm-svn: 146076

Skip two looking up at BlockChain.

llvm-svn: 146053

generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026

Zap unnecessary isIntDivCheap() check.  PR11485.  No testcase because this doesn't affect any in-tree target.

llvm-svn: 146015

llvm-svn: 146004

llvm-svn: 146001

This flag is used when bundling machine instructions.  It indicates
whether the operand reads a value defined inside or outside its bundle.

llvm-svn: 145997

llvm-svn: 145996

llvm-svn: 145995

- Remove unused types/fields.
- Add some constantness.

llvm-svn: 145993

1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975

llvm-svn: 145965

llvm-svn: 145944

llvm-svn: 145943

llvm-svn: 145903

The new register allocator is much more able to split back up ranges too constrained by register classes.

Fixes <rdar://problem/10466609>

llvm-svn: 145899

llvm-svn: 145897

llvm-svn: 145893

This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

llvm-svn: 145889

Add support for vectors of pointers.

llvm-svn: 145801

not get there any other way.

llvm-svn: 145789

Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781

-3% on ARMDissasembler.cpp.

llvm-svn: 145773

change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714

make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop

llvm-svn: 145677

Missing file from r145629.

llvm-svn: 145634

llvm-svn: 145629

attempt.  

llvm-svn: 145425

llvm-svn: 145420

non_lazy_symbol_pointers section (__IMPORT,__pointers). Ignore the 'hidden' part
since that will place it in the wrong section.
<rdar://problem/10443720>

llvm-svn: 145356

Make SelectionDAG::InferPtrAlignment use llvm::ComputeMaskedBits instead of duplicating the logic for globals.  Make llvm::ComputeMaskedBits handle GlobalVariables slightly more aggressively, to match what InferPtrAlignment knew how to do.

llvm-svn: 145304

Conservatively returns zero when the GV does not specify an alignment nor is it
initialized. Previously it returns ABI alignment for type of the GV. However, if
the type is a "packed" type, then the under-specified alignments is attached to
the load / store instructions. In that case, the alignment of the type cannot be
trusted.
rdar://10464621

llvm-svn: 145300

than ABI alignment. These are loads / stores from / to "packed" data structures.
Their alignments are intentionally under-specified.

rdar://10301431

llvm-svn: 145273

llvm-svn: 145267

llvm-svn: 145263

fallthrough) in cases where we might fail to rotate an exit to an outer
loop onto the end of the loop chain.

Having *some* rotation, but not performing this rotation, is the primary
fix of thep performance regression with -enable-block-placement for
Olden/em3d (a whopping 30% regression). Still working on reducing the
test case that actually exercises this and the new rotation strategy out
of this code, but I want to check if this regresses other test cases
first as that may indicate it isn't the correct fix.

llvm-svn: 145195