avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059

The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024

case for DCLO and DCLZ.

llvm-svn: 147022

llvm-svn: 147021

llvm-svn: 147019

DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017

instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015

llvm-svn: 147014

llvm-svn: 147013

llvm-svn: 147012

nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008

llvm-svn: 147007

llvm-svn: 147005

llvm-svn: 147004

llvm-svn: 147003

only when the target ABI is N64.

llvm-svn: 147001

MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999

llvm-svn: 146996

llvm-svn: 146995

only when the target ABI is N64. 

llvm-svn: 146992

likely to stay either way that discussion ends up resolving itself.

llvm-svn: 146966

llvm-svn: 146960

patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900

llvm-svn: 146896

direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893

llvm-svn: 146889

This change reduces the number of instructions generated.

For example, 
(load (add (sub $n0, $n1), (MipsLo got(s))))

results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)

Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)

llvm-svn: 146888

emission is not supported yet, but a patch that adds the support should follow
soon.

llvm-svn: 146572

in a 16-bit field.

llvm-svn: 146469

undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.

Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.

Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.

llvm-svn: 146466

subdirectories to traverse into.
 - Originally I wanted to avoid this and just autoscan, but this has one key
   flaw in that new subdirectories can not automatically trigger a rerun of the
   llvm-build tool. This is particularly a pain when switching back and forth
   between trees where one has added a subdirectory, as the dependencies will
   tend to be wrong. This will also eliminates FIXME implicitly.

llvm-svn: 146436

-relocation-model=static.

llvm-svn: 146432

llvm-svn: 146431

llvm-svn: 146409

llvm-svn: 146340

llvm-svn: 146232

specified.

llvm-svn: 146229

MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.

llvm-svn: 146183

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175

RDHWR. 

llvm-svn: 146101