llvm-svn: 25660

Global Variable information is now pulled from "llvm.dbg.globals"

llvm-svn: 25655

llvm-svn: 25653

llvm-svn: 25652

llvm-svn: 25649

llvm-svn: 25645

fix stack corruption! Previously, 16-byte whole-FP-register stores were
being treated as needing only 8 bytes (though they were 16 byte aligned.)

This should fix a bunch of tests - anyone have any comments, though?

  - in Target.td , SpillSize and SpillAlignment seem dead - is this what
    Size and Alignment do now?
  - in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
    DeclaredSpillAlignment seem dead.
  - there are a bunch of comments here and there that don't clearly
    distinguish between 'size' and 'spillsize' etc. hmm.

llvm-svn: 25644

llvm-svn: 25643

llvm-svn: 25642

llvm-svn: 25641

llvm-svn: 25640

llvm-svn: 25639

llvm-svn: 25638

llvm-svn: 25637

one use. This allows more CMOV instructions.

llvm-svn: 25634

llvm-svn: 25633

llvm-svn: 25631

chain successors.

llvm-svn: 25630

SDNPOutFlag, and SDNPOptInFlag instead.

llvm-svn: 25629

llvm-svn: 25626

llvm-svn: 25623

llvm-svn: 25621

llvm-svn: 25620

llvm-svn: 25619

llvm-svn: 25618

llvm-svn: 25617

llvm-svn: 25614

llvm-svn: 25613

llvm-svn: 25610

llvm-svn: 25609

already in order. Thanks Jim for pointing it out.

llvm-svn: 25608

llvm-svn: 25607

Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606

llvm-svn: 25605

llvm-svn: 25604

llvm-svn: 25603

llvm-svn: 25602

llvm-svn: 25601

llvm-svn: 25600

preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.

llvm-svn: 25599