Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.

llvm-svn: 198284

llvm-svn: 198281

[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.

llvm-svn: 198280

llvm-svn: 198279

Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.

llvm-svn: 198278

Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277

Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198276

Patch by Ilia Filippov!

llvm-svn: 198267

Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.

llvm-svn: 198265

llvm-svn: 198263

llvm-svn: 198262

llvm-svn: 198258

llvm-svn: 198257

lib/Support/ThreadLocal.cpp:53:15: error: typedef 'SIZE_TOO_BIG' locally defined but not used [-Werror=unused-local-typedefs]
   typedef int SIZE_TOO_BIG[sizeof(pthread_key_t) <= sizeof(data) ? 1 : -1];

Done the C++11 way, switching on and using LLVM_STATIC_ASSERT() instead of LLVM_ATTRIBUTE_UNUSED.

llvm-svn: 198255

llvm-svn: 198254

llvm-svn: 198241

Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198238

Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235

llvm-svn: 198233

      r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front.
      r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer.
      r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo.

with a fix to use integer 0 for DW_AT_low_pc since the relocation to the text section symbol was causing issues with COFF. Accordingly remove addLocalLabelAddress and machinery since we're not currently using it.

llvm-svn: 198222

  r198196: Use a pointer to keep track of the skeleton unit for each normal unit and construct it up front.
  r198199: Reapply r198196 with a fix to zero initialize the skeleton pointer.
  r198202: Fix aranges and split dwarf by ensuring that the symbol and relocation back to the compile unit from the aranges section is to the skeleton unit and not the one in the dwo.

They could be reproducible with explicit target.

  llvm/lib/MC/WinCOFFObjectWriter.cpp:224: bool {anonymous}::COFFSymbol::should_keep() const: Assertion `Section->Number != -1 && "Sections with relocations must be real!"' failed.

llvm-svn: 198208

back to the compile unit from the aranges section is to the skeleton
unit and not the one in the dwo.

Do this by adding a method to grab a forwarded on local sym and local
section by querying the skeleton if one exists and using that. Add
a few tests to verify the relocations are back to the correct section.

llvm-svn: 198202

llvm-svn: 198201

llvm-svn: 198199

each normal unit" as it seems to be causing problems in the asan tests.

llvm-svn: 198197

and construct it up front. Add address ranges at the end and a helper
routine so that we're not needlessly using an indirction in the case
of split dwarf.

Update testcases according to the new ordering of attributes on
the compile unit.

llvm-svn: 198196

llvm-svn: 198194

llvm-svn: 198193

llvm-svn: 198192

For AArch64 backend, if DAGCombiner see "sext(setcc)", it will
combine them together to a single setcc with extended value type.
Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to
create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1,
DAGcombiner will create wrong node and get wrong code emitted.

llvm-svn: 198190

E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b

llvm-svn: 198188

(unittests/ExecutionEngine/JIT/CMakeLists.txt is still missing for now, since
it handles export files in a strange way: It generates a .exports file from a
.def file instead of the other way round.)

llvm-svn: 198183

The DPR and SPR register lists are also register lists.  Furthermore, the
registers need not be checked individually since the register type can be
checked via the list kind.  Use that to simplify the logic and fix the incorrect
assertion.

llvm-svn: 198174

In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

llvm-svn: 198172

llvm-svn: 198171

The vstm family of VFP instructions belong to the VFP store itinerary class, not
the VFP load itinerary class.

llvm-svn: 198170

llvm-svn: 198162

This plugs a memory leak in ARM's FastISel by storing the GV in Module so that
it's reclaimed.
PR17978

llvm-svn: 198160

[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
 This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157

[SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
 This makes the sparc backend to generate Sparc64 ABI compliant code.

llvm-svn: 198149