from DYNAMIC_STACKALLOC.

Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added.  They
will be custom emitted to inject the actual stack handling code.

Patch by Sanjoy Das.

llvm-svn: 138814

X86. Modify the pass added in the previous patch to call this new
code.

This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required

Patch by Sanjoy Das.

llvm-svn: 138812

-segmented-stacks.
Patch by Sanjoy Das!

llvm-svn: 138811

Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810

When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does.

llvm-svn: 138809

llvm-svn: 138807

llvm-svn: 138806

Eli added this in revision 132695.

llvm-svn: 138805

This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!

llvm-svn: 138804

arguments as before), unset CR1EQ otherwise.

llvm-svn: 138802

Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138799

Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138798

Patch supplied by Liu (projlc@gmail.com)

llvm-svn: 138797

llvm-svn: 138796

Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

llvm-svn: 138795

I don't currently have a good testcase for this; will try to get one
tomorrow.  <rdar://problem/10032939>

llvm-svn: 138794

register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791

llvm-svn: 138782

llvm-svn: 138781

llvm-svn: 138780

llvm-svn: 138779

llvm-svn: 138778

llvm-svn: 138777

llvm-svn: 138773

llvm-svn: 138771

Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32.  This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly.  Fixes PR10802.

llvm-svn: 138768

llvm-svn: 138767

Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758.  Fixes ary3 from the nightly test suite.

llvm-svn: 138766

llvm-svn: 138764

llvm-svn: 138760

llvm-svn: 138759

addrmode_imm12 and addrmode2_offset encode their immediate values differently.  Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12.  Should fix a number of nightly test failures.

llvm-svn: 138758

Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.

llvm-svn: 138756

llvm-svn: 138754

llvm-svn: 138752

llvm-svn: 138751

llvm-svn: 138750

llvm-svn: 138749

llvm-svn: 138748

llvm-svn: 138747