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  1. Jan 15, 2012
  3. Jan 14, 2012
  5. Jan 13, 2012
  7. Jan 12, 2012
  9. Jan 11, 2012
    • Jakob Stoklund Olesen's avatar
      Sink spillInterferences into RABasic. · 73edbf16
      Jakob Stoklund Olesen authored 
      This helper method is too simplistic for RAGreedy.

llvm-svn: 147976
      73edbf16
    • Jakob Stoklund Olesen's avatar
      Cleanup. · 06ec4203
      Jakob Stoklund Olesen authored 
      llvm-svn: 147975
      06ec4203
    • Jakob Stoklund Olesen's avatar
      Move RegAllocBase into its own cpp file separate from RABasic. · a818d804
      Jakob Stoklund Olesen authored 
      No functional change.

llvm-svn: 147972
      a818d804
    • Nadav Rotem's avatar
      On AVX, we can load v8i32 at a time. The bug happens when two uneven loads are used. · b5ce6ee8
      Nadav Rotem authored 
      When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 
and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen 
the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX.

llvm-svn: 147964
      b5ce6ee8
    • Chandler Carruth's avatar
      Teach the X86 instruction selection to do some heroic transforms to · 55b2cdee
      Chandler Carruth authored 
      detect a pattern which can be implemented with a small 'shl' embedded in
the addressing mode scale. This happens in real code as follows:

  unsigned x = my_accelerator_table[input >> 11];

Here we have some lookup table that we look into using the high bits of
'input'. Each entity in the table is 4-bytes, which means this
implicitly gets turned into (once lowered out of a GEP):

  *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2));

The shift right followed by a shift left is canonicalized to a smaller
shift right and masking off the low bits. That hides the shift right
which x86 has an addressing mode designed to support. We now detect
masks of this form, and produce the longer shift right followed by the
proper addressing mode. In addition to saving a (rather large)
instruction, this also reduces stalls in Intel chips on benchmarks I've
measured.

In order for all of this to work, one part of the DAG needs to be
canonicalized *still further* than it currently is. This involves
removing pointless 'trunc' nodes between a zextload and a zext. Without
that, we end up generating spurious masks and hiding the pattern.

llvm-svn: 147936
      55b2cdee
    • Jakob Stoklund Olesen's avatar
      Detect when a value is undefined on an edge to a landing pad. · 8b1d023a
      Jakob Stoklund Olesen authored 
      Consider this code:

int h() {
  int x;
  try {
    x = f();
    g();
  } catch (...) {
    return x+1;
  }
  return x;
}

The variable x is undefined on the first edge to the landing pad, but it
has the f() return value on the second edge to the landing pad.

SplitAnalysis::getLastSplitPoint() would assume that the return value
from f() was live into the landing pad when f() throws, which is of
course impossible.

Detect these cases, and treat them as if the landing pad wasn't there.
This allows spill code to be inserted after the function call to f().

<rdar://problem/10664933>

llvm-svn: 147912
      8b1d023a
    • Jakob Stoklund Olesen's avatar
      Exclusively use SplitAnalysis::getLastSplitPoint(). · 67aec124
      Jakob Stoklund Olesen authored 
      Delete the alternative implementation in LiveIntervalAnalysis.

These functions computed the same thing, but SplitAnalysis caches the
result.

llvm-svn: 147911
      67aec124
    • Evan Cheng's avatar
      Avoid CSE of instructions which define physical registers across MBBs unless · d9725a38
      Evan Cheng authored 
      the physical registers are not allocatable.

llvm-svn: 147902
      d9725a38
  11. Jan 10, 2012
  13. Jan 08, 2012