- Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.

llvm-svn: 85682

previously running CodePlacementOpt. Also print headers before
each dump in -print-machineinstrs mode, so that it's clear which
dump is which.

llvm-svn: 85681

llvm-svn: 85680

block with a blockaddress still referring to it' replace the invalid 
blockaddress with a new blockaddress(@func, null) instead of a 
inttoptr(1).

This changes the bitcode encoding format, and still needs codegen 
support (this should produce a non-zero value, referring to the entry
block of the function would also be quite reasonable).

llvm-svn: 85678

llvm-svn: 85676

is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675

llvm-svn: 85674

llvm-svn: 85673

SDKROOT can refer to the target when we're building for the host.

llvm-svn: 85672

llvm-svn: 85671

auto-update the DominatorTree because it doesn't keep the DominatorTree
current while it works.

llvm-svn: 85670

llvm-svn: 85668

MergeBlockIntoPredecessor. This makes SimplifyCFG slightly more aggressive,
and makes it unnecessary for LoopUnroll to have its own copy of this code.

llvm-svn: 85667

clears out more information than just the stored backedge taken count.

llvm-svn: 85664

the new common CodeMetrics code.

llvm-svn: 85663

llvm-svn: 85662

llvm-svn: 85661

llvm-svn: 85660

LoopUnrollPass.cpp, for consistency with other passes which are
similarly split.

llvm-svn: 85659

to unfold loop-invariant loads.

llvm-svn: 85657

underlying alias call even for non-identified-object values.

llvm-svn: 85656

llvm-svn: 85655

that uses this information knows to behave conservatively.

llvm-svn: 85654

llvm-svn: 85653

llvm-svn: 85648

It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.

llvm-svn: 85643

llvm-svn: 85641

llvm-svn: 85640

llvm-svn: 85639

results. This works around a problem affecting targets which rely on
MVT::Flag to handle physical register defs.

llvm-svn: 85638

llvm-svn: 85637

llvm-svn: 85636

llvm-svn: 85635

PHI operands by the predecessor order, sort them by the order used by the
first PHI in the block. This is still suffucient to expose duplicates.

llvm-svn: 85634

Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.

llvm-svn: 85632

llvm-svn: 85630

around, then zap them.  This is analogous to dangling constantexprs hanging
off functions.

llvm-svn: 85627

This reduces codesize on a variety of codes by 1-2% on x86-64. It also
helps clean up after SSAUpdater.

llvm-svn: 85626

llvm-svn: 85625

llvm-svn: 85624