Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).

llvm-svn: 102485

ForcedAlignBits argument, tweaking the single client of it.

llvm-svn: 102484

llvm-svn: 102483

llvm-svn: 102482

llvm-svn: 102481

of dependence and define trap values in terms of dependence, instead
of trying to cover the concept with a flurry of ad-hoc rules.

The dependence model isn't complete yet, but it's already much more
rigorous than the description it replaces.

llvm-svn: 102479

llvm-svn: 102478

llvm-svn: 102477

to not increase the alignment of globals with an assigned
alignment and section.

llvm-svn: 102476

it is not generally valid for targets to overalign
them when an alignment is specified.

llvm-svn: 102474

llvm-svn: 102472

llvm-svn: 102470

llvm-svn: 102468

llvm-svn: 102467

llvm-svn: 102463

llvm-svn: 102456

- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x)

llvm-svn: 102455

Identify when a lexical scope is split in to multiple instruction ranges. Emit such ranges using DW_AT_ranges.
This patch fixes bug (PR6894) introduced by previous version of this patch.

llvm-svn: 102454

llvm-svn: 102453

should fix some "g++.dg-struct-layout-1" failures, 
rdar://7886017

llvm-svn: 102421

llvm-svn: 102418

llvm-svn: 102417

of the dbg testsuite regressions.  I don't think this is
really the right fix; this change exposed an existing problem
upstream somewhere.

llvm-svn: 102410

*not* declarations to *not* be placed in the "preserve" list.
<rdar://problem/7870735>

llvm-svn: 102405

in ISel fixed it.

llvm-svn: 102404

add a version of createLowerInvokePass that allows the client
to specify whether it wants "expensive" or "cheap" lowering.

Patch by Alex Mac!

llvm-svn: 102402

llvm-svn: 102401

otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505

llvm-svn: 102400

traps flowing through memory references, add some text to
better cover phi nodes and externally-visible side effects,
add an example of instructions being control-dependent
on a trap value, and reword some of the existing trap rules.

llvm-svn: 102399

Radar 7896289

llvm-svn: 102396

to print the operand.

llvm-svn: 102395

llvm-svn: 102394

doesn't dominate the header is needed, don't check whether the increment
expression has computable loop evolution. While the operands of an
addrec are required to be loop-invariant, they're not required to 
dominate any part of the loop. This fixes PR6914.

llvm-svn: 102389

llvm-svn: 102387

intrinsics have volatile semantics in addition to the load and store
instructions.  

llvm-svn: 102384

onto control-dependent instructions.

llvm-svn: 102381

llvm-svn: 102380

llvm-svn: 102378

llvm-svn: 102376

llvm-svn: 102373