llvm-svn: 147071

llvm-svn: 147069

necessary.  Please chime in if I'm mistaken.

llvm-svn: 147065

llvm-svn: 147064

Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer
for buffer management. Switched the code to make use of the trailing
'0' that MemoryBuffer guarantees where it makes sense.

llvm-svn: 147063

Other targets will follow shortly.

llvm-svn: 147060

avoid including ADT/Triple.h in many places when the target specific bits are
moved.

llvm-svn: 147059

side when the target specific bits are moved to the Target directory.

llvm-svn: 147053

llvm-svn: 147049

Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.

llvm-svn: 147046

llvm-svn: 147045

call site of an intrinsic is also not an inline candidate. While here, make it
more obvious that this code ignores all intrinsics. Noticed by inspection!

llvm-svn: 147037

llvm-svn: 147036

llvm-svn: 147032

llvm-svn: 147028

llvm-svn: 147025

The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024

case for DCLO and DCLZ.

llvm-svn: 147022

llvm-svn: 147021

llvm-svn: 147019

DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017

instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015

llvm-svn: 147014

llvm-svn: 147013

llvm-svn: 147012

the build bot in some cases.  The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type.  It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext.  We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.

Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is 
pretty great that way.

llvm-svn: 147010

llvm-svn: 147009

nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008

llvm-svn: 147007

llvm-svn: 147005

llvm-svn: 147004

llvm-svn: 147003

only when the target ABI is N64.

llvm-svn: 147001

llvm-svn: 147000

MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999

Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

llvm-svn: 146997

llvm-svn: 146996

llvm-svn: 146995

only when the target ABI is N64. 

llvm-svn: 146992

llvm-svn: 146990