- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246

llvm-svn: 27245

- Other shuffle related fixes.

llvm-svn: 27244

The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240

llvm-svn: 27239

llvm-svn: 27225

llvm-svn: 27223

llvm-svn: 27222

llvm-svn: 27221

llvm-svn: 27220

llvm-svn: 27219

* Bug fixes.

llvm-svn: 27218

llvm-svn: 27212

llvm-svn: 27211

- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210

intrinsics as such.

llvm-svn: 27200

llvm-svn: 27180

llvm-svn: 27174

llvm-svn: 27167

manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156

llvm-svn: 27152

llvm-svn: 27150

llvm-svn: 27120

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27109

llvm-svn: 27103

llvm-svn: 27102

llvm-svn: 27096

llvm-svn: 27095

llvm-svn: 27094

llvm-svn: 27091

llvm-svn: 27087

llvm-svn: 27083

llvm-svn: 27081

llvm-svn: 27056

llvm-svn: 27049

llvm-svn: 27044

llvm-svn: 27040

llvm-svn: 27039

llvm-svn: 27024