llvm-svn: 146780

The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.

<rdar://problem/10594653>

llvm-svn: 146767

Hexatridecimal was added in r139695.

And fix the unittest that now triggers the assert.

llvm-svn: 146754

This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.

When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.

llvm-svn: 146751

Reenable the tests.

llvm-svn: 146750

llvm-svn: 146744

The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

llvm-svn: 146739

llvm-svn: 146735

autorenamed version of the other.   This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.

llvm-svn: 146728

Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.

llvm-svn: 146726

llvm-svn: 146724

No need for an explicit test case for an unsupported combination of options.

llvm-svn: 146721

llvm-svn: 146714

llvm-svn: 146710

Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly.  PR11586.

llvm-svn: 146709

llvm-svn: 146702

Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value.  (This is just to be safe; I don't think this actually causes any issues in practice.)

llvm-svn: 146700

llvm-svn: 146699

[asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports.

llvm-svn: 146698

llvm-svn: 146692

llvm-svn: 146691

The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689

[asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part.

llvm-svn: 146688

llvm-svn: 146686

llvm-svn: 146685

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684

Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.

llvm-svn: 146671

Patch by Kyriakos Georgiou!

llvm-svn: 146670

llvm-svn: 146665

llvm-svn: 146664

Patch by Kyriakos Georgiou.

llvm-svn: 146656

llvm-svn: 146639

Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.

llvm-svn: 146630

llvm-svn: 146627

rdar://10566486

llvm-svn: 146625

These can be reduced to "~cond & x" or "~cond | x"

llvm-svn: 146624

Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls.  These are already marked as illegal by default.

llvm-svn: 146623

Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header).  Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads.  PR11575.

llvm-svn: 146621

Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order.

llvm-svn: 146617