Commits · 366857a23ab44247d5c8651bb067920b0306626b · Roger Ferrer / llvm-epi-0.8 · GitLab

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Apr 11, 2018
- [MIPS GlobalISel] Select add i32, i32 · 366857a2
  Petar Jovanovic authored Apr 11, 2018
  366857a2
- [AMDGPU] Fix lowering enqueue_kernel · 9381ae97
  Yaxun Liu authored Apr 11, 2018
  9381ae97
- Revert "[AMDGPU] Ensure there are enough registers for wave dispatch" · 8ca33bfc
  Tim Renouf authored Apr 11, 2018
  8ca33bfc
- [AArch64][AsmParser] Split index parsing from vector list. · c88f9a1a
  Sander de Smalen authored Apr 11, 2018
  c88f9a1a
- [AMDGPU] Ensure there are enough registers for wave dispatch · f26b7234
  Tim Renouf authored Apr 11, 2018
  f26b7234
- [X86] Add variable shuffle schedule classes · 89c8a10f
  Simon Pilgrim authored Apr 11, 2018
  89c8a10f
- [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32 · fc715551
  Dmitry Preobrazhensky authored Apr 11, 2018
  fc715551
- [AArch64] Fix regression after r329691 · 6463922e
  Francis Visoiu Mistrih authored Apr 11, 2018
  6463922e
- [ARM] FP16 VSEL codegen · ac96d7c4
  Sjoerd Meijer authored Apr 11, 2018
  ac96d7c4
- [AArch64][AsmParser] Unify code for parsing Neon/SVE vectors. · 73937b7c
  Sander de Smalen authored Apr 11, 2018
  73937b7c
- [X86] Remove 128/256-bit masked pmaddubsw and pmaddwd intrinsics. Replace... · 9507fa35
  Craig Topper authored Apr 11, 2018
  9507fa35
- [X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit... · ee2c1dea
  Craig Topper authored Apr 11, 2018
  ee2c1dea
- GOTPCREL references must always use RIP. · d693093a
  Sriraman Tallam authored Apr 10, 2018
  d693093a
- AMDGPU: enable 128-bit for local addr space under an option · a9a58fa2
  Marek Olsak authored Apr 10, 2018
  a9a58fa2
Apr 10, 2018
- [AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass. · 5696e075
  Geoff Berry authored Apr 10, 2018
  5696e075
- Recommit r329716 "Add missing nullptr check before getSection() to... · a450ed23
  Jessica Paquette authored Apr 10, 2018
  a450ed23
- [AArch64] Fix isel failure when BUILD_PAIR nodes are left over. · e27d5016
  Amara Emerson authored Apr 10, 2018
  e27d5016
- [X86] Split up -march=icelake to -client & -server · 213edc4a
  Gabor Buella authored Apr 10, 2018
  213edc4a
- [X86] Change the name string for the newly add DF flag register to 'dirflag'... · 44242854
  Craig Topper authored Apr 10, 2018
  44242854
- Revert 329716 "Add missing nullptr check before getSection() to... · c140bbdd
  Jessica Paquette authored Apr 10, 2018
  c140bbdd
- Revert r329611, "AArch64: Allow offsets to be folded into addresses with ELF." · a7d936f0
  Peter Collingbourne authored Apr 10, 2018
  a7d936f0
- Add missing nullptr check to AArch64MachObjectWriter::recordRelocation · e4b90d82
  Jessica Paquette authored Apr 10, 2018
  e4b90d82
- AMDGPU/MC: Allow disassembling without symbol info · b1c3b22b
  Nicolai Haehnle authored Apr 10, 2018
  b1c3b22b
- Fix spelling. NFC. · af7519e9
  Chad Rosier authored Apr 10, 2018
  af7519e9
- Fix whitespace indentation. NFCI. · 95f94111
  Simon Pilgrim authored Apr 10, 2018
  95f94111
- [X86] Disable SGX for Skylake Server · 3eab22d8
  Gabor Buella authored Apr 10, 2018
  3eab22d8
- [AArch64] Use FP to access the emergency spill slot · f2c22050
  Francis Visoiu Mistrih authored Apr 10, 2018
  f2c22050
- [AMDGPU] For OS type AMDPAL, fixed scratch on compute shader · 7190a469
  Tim Renouf authored Apr 10, 2018
  7190a469
- AArch64: diagnose unpredictable store-exclusive instructions · 6a1c51bf
  Tim Northover authored Apr 10, 2018
  6a1c51bf
- [X86][Broadwell] HWPort5 should not be added to BroadwellModelProcResources. · 486358c1
  Andrea Di Biagio authored Apr 10, 2018
  486358c1
- [AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions. · f974e255
  Sander de Smalen authored Apr 10, 2018
  f974e255
- [MC][TableGen] Add optional libpfm counter names for ProcResUnits. · b449379e
  Clement Courbet authored Apr 10, 2018
  b449379e
- [AArch64][SVE] Asm: Add support for SVE INDEX instructions. · 30fda45c
  Sander de Smalen authored Apr 10, 2018
  30fda45c
- [x86] Model the direction flag (DF) separately from the rest of EFLAGS. · 0ca3bd07
  Chandler Carruth authored Apr 10, 2018
  0ca3bd07
- [X86] Prevent folding loads with 64-bit ANDs with immediates that fit in 32-bits. · 7e42af87
  Craig Topper authored Apr 10, 2018
  7e42af87
- [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues. · 19618fc6
  Chandler Carruth authored Apr 10, 2018
  19618fc6
- ShadowCallStack/x86_64: Ignore pseudo-machine instructions · 0cdc6ec5
  Vlad Tsyrklevich authored Apr 10, 2018
  0cdc6ec5
Apr 09, 2018
- [globalisel][legalizerinfo] Add support for the Lower action in... · 5281b02e
  Daniel Sanders authored Apr 09, 2018
  5281b02e
- AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header · 6183065b
  Konstantin Zhuravlyov authored Apr 09, 2018
  6183065b
- [X86] Don't use Lower512IntUnary to split bitcasts with v32i16/v64i8 types on... · 47b2f9d8
  Craig Topper authored Apr 09, 2018
  47b2f9d8