instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513

the VST pseudos.  The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.

llvm-svn: 113473

llvm-svn: 113463

llvm-svn: 113461

llvm-svn: 113459

operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

llvm-svn: 113456

llvm-svn: 113455

for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.

llvm-svn: 113453

For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.

llvm-svn: 113452

llvm-svn: 113442

llvm-svn: 113440

llvm-svn: 113436

llvm-svn: 113435

llvm-svn: 113417

Re-running some nightly testers w/ it enabled to verify.

llvm-svn: 113399

pointer was intended. rdar://8401980

llvm-svn: 113394

llvm-svn: 113387

option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).

llvm-svn: 113366

llvm-svn: 113365

implementation's job to check for and lex the EndOfStatement
marker.

llvm-svn: 113347

ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.

llvm-svn: 113345

llvm-svn: 113338

llvm-svn: 113337

related. (attempt deux, complete w/ test update this time)

llvm-svn: 113333

llvm-svn: 113332

llvm-svn: 113331

present in the function and thus whether aligned load/store instructions can
be used.

llvm-svn: 113323

llvm-svn: 113322

register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).

rdar://8394087

llvm-svn: 113297

llvm-svn: 113289

llvm-svn: 113255

of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178

llvm-svn: 113165

into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.

llvm-svn: 113163

pattern, so there is no need to define a matching function.

llvm-svn: 113122

llvm-svn: 113119

llvm-svn: 113073

"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."

r112986 fixed a latent bug exposed by the above.

llvm-svn: 112989

alignment should be performed. Otherwise dynamic realignment may trigger
when the register allocator has already used the frame pointer as a general
purpose register. That is, we need to make sure that the list of reserved
registers doesn't change after register allocation.

llvm-svn: 112986

instructions prior to regalloc.  Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.

llvm-svn: 112983