distinguish between objects and register names, now we can have stuff
with names like "f84", "in6" etc etc.

this should fix one or two tests

llvm-svn: 26232

We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.

llvm-svn: 26231

transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

llvm-svn: 26226

Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).

llvm-svn: 26224

llvm-svn: 26222

llvm-svn: 26217

it, because this:

.bss
X:
.byte 0

results in the assembler warning: "initialization in bss segment".  Annoying.

llvm-svn: 26204

The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.

llvm-svn: 26202

llvm-svn: 26197

llvm-svn: 26196

llvm-svn: 26193

llvm-svn: 26192

llvm-svn: 26186

emit it (instead of .space), saving a bit of space in the .o file.

For example:
int foo[100];
int bar[100] = {};

when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space.  The X86 backend can also do this on darwin.

llvm-svn: 26185

llvm-svn: 26183

XMM registers were not being handled.

llvm-svn: 26182

llvm-svn: 26181

llvm-svn: 26180

llvm-svn: 26179

llvm-svn: 26174

llvm-svn: 26173

maxStoresPerMemMove. Although the last one is not used.

llvm-svn: 26172

llvm-svn: 26169

llvm-svn: 26150

llvm-svn: 26148

CALLSEQ_START nodes.

llvm-svn: 26143

llvm-svn: 26142

PowerPC/and-imm.ll

llvm-svn: 26136

fix storing booleans (grawp missed this one)

llvm-svn: 26120

now short immediates will get matched (previously constants were all
triggering movl 64bit imm fat instructions)

llvm-svn: 26119

X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.

llvm-svn: 26117

llvm-svn: 26111

llvm-svn: 26110

intrinsics.

Autogen frameindex matcher

llvm-svn: 26107

llvm-svn: 26106

llvm-svn: 26105

llvm-svn: 26096

llvm-svn: 26091

llvm-svn: 26090

llvm-svn: 26085