llvm-svn: 59802

llvm-svn: 59801

a subtract is cheaper than a multiply. This generalizes an existing transform.

llvm-svn: 59800

llvm-svn: 59792

(a) Fix bgs 3052, 3057
(b) Incorporate Duncan's suggestions re: i1 promotion
(c) Indentation updates.

llvm-svn: 59790

llvm-svn: 59788

llvm-svn: 59787

llvm-svn: 59786

llvm-svn: 59785

llvm-svn: 59783

less mysterious.

llvm-svn: 59782

because the boolean it returns to indicate an overflow may not be treated like
as a flag. It could be stored to memory, for instance.

llvm-svn: 59780

"ISD::ADDO". ISD::ADDO is lowered into a target-independent form that does the
addition and then checks if the result is less than one of the operands. (If it
is, then there was an overflow.)

llvm-svn: 59779

llvm-svn: 59778

llvm-svn: 59777

schedulers. This doesn't have much immediate impact because
targets that use these schedulers by default don't yet provide
pipeline information.

This code also didn't have the benefit of register pressure
information. Also, removing it will avoid problems with list-burr
suddenly starting to do latency-oriented scheduling on x86 when we
start providing pipeline data, which would increase spilling.

llvm-svn: 59775

some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.

llvm-svn: 59761

condition in an addition operation.

llvm-svn: 59760

the RR scheduler actually does look at latency values, but it
doesn't use a hazard recognizer so it has no way to know when
a no-op is needed, as opposed to just stalling and incrementing
the cycle count.

llvm-svn: 59759

llvm-svn: 59758

inlining function, then increase the stack protection level on the inlining
function.

llvm-svn: 59757

MachineInstr scheduling DAG, meaning they implicitly depend on all
preceding defs. This fixes Benchmarks/Shootout-C++/except and
Regression/C++/EH/simple_rethrow in
  -relocation-model=pic -disable-post-RA-scheduler=false
mode.

llvm-svn: 59747

llvm-svn: 59746

llvm-svn: 59745

(a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy.
(b) Remove truncated stores that will never be used.
(c) Add initial support for __muldi3 as a libcall.

llvm-svn: 59734

llvm-svn: 59727

llvm-svn: 59720

llvm-svn: 59718

promote), fix signed conversion of indexed offsets.

llvm-svn: 59707

llvm-svn: 59705

llvm-svn: 59703

llvm-svn: 59702

list-tdrr schedulers into a common base class.

llvm-svn: 59701

dedicated "fast" scheduler in -fast mode instead, which is
faster. This speeds up llc -fast by a few percent on some
testcases -- the speedup only happens for code not handled by
fast-isel.

llvm-svn: 59700

the list-burr scheduler so that it can be used by the list-tdrr
scheduler too.

llvm-svn: 59698

- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.

llvm-svn: 59697

llvm-svn: 59696

llvm-svn: 59692

extend it a bit, and make use of it in all schedulers, to
ensure consistent checking.

llvm-svn: 59689

llvm-svn: 59688