llvm-svn: 24121

llvm-svn: 24120

1. Embed and not inherit vector for NodeGroup.

2. Iterate operands and not uses (performance.)

3. Some long pending comment changes.

llvm-svn: 24119

llvm-svn: 24118

llvm-svn: 24117

a special case hack for X86, make the hack more general: if an incoming argument
register is not used in any block other than the entry block, don't copy it to
a vreg.  This helps us compile code like this:

%struct.foo = type { int, int, [0 x ubyte] }
int %test(%struct.foo* %X) {
        %tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100
        %tmp = load ubyte* %tmp1                ; <ubyte> [#uses=1]
        %tmp2 = cast ubyte %tmp to int          ; <int> [#uses=1]
        ret int %tmp2
}

to:

_test:
        lbz r3, 108(r3)
        blr

instead of:

_test:
        lbz r2, 108(r3)
        or r3, r2, r2
        blr

The (dead) copy emitted to copy r3 into a vreg for extra-block uses was
increasing the live range of r3 past the load, preventing the coallescing.

This implements CodeGen/PowerPC/reg-coallesce-simple.ll

llvm-svn: 24115

llvm-svn: 24112

generating results in vregs that will need them.  In the case of something
like this:  CopyToReg((add X, Y), reg1024), we no longer emit code like
this:

   reg1025 = add X, Y
   reg1024 = reg 1025

Instead, we emit:

   reg1024 = add X, Y

Whoa! :)

llvm-svn: 24111

llvm-svn: 24110

llvm-svn: 24109

llvm-svn: 24108

llvm-svn: 24107

This implements test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll,
producing:

_foo:
        slwi r2, r3, 1
        subfic r3, r2, 63
        blr

instead of:

_foo:
        mulli r2, r3, -2
        addi r3, r2, 63
        blr

llvm-svn: 24106

llvm-svn: 24103

When inserting code for an addrec expression with a non-unit stride, be
more careful where we insert the multiply.  In particular, insert the multiply
in the outermost loop we can, instead of the requested insertion point.

This allows LSR to notice the mul in the right loop, reducing it when it gets
to it.  This allows it to reduce the multiply, where before it missed it.

This happens quite a bit in the test suite, for example, eliminating 2
multiplies in art, 3 in ammp, 4 in apsi, reducing from 1050 multiplies to
910 muls in galgel (!), from 877 to 859 in applu, and 36 to 30 in bzip2.

This speeds up galgel from 16.45s to 16.01s, applu from 14.21 to 13.94s and
fourinarow from 66.67s to 63.48s.

This implements Transforms/LoopStrengthReduce/nested-reduce.ll

llvm-svn: 24102

llvm-svn: 24099

llvm-svn: 24098

llvm-svn: 24097

llvm-svn: 24096

building the itanium backend.

llvm-svn: 24095

DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream

llvm-svn: 24094

llvm-svn: 24093

llvm-svn: 24092

llvm-svn: 24091

infrastructure and the simple isels have been removed.

llvm-svn: 24090

llvm-svn: 24089

llvm-svn: 24088

llvm-svn: 24087

llvm-svn: 24086

llvm-svn: 24085

llvm-svn: 24084

llvm-svn: 24083

llvm-svn: 24082

This allows us to turn code like malloc(4*x+4) -> malloc int, (x+1)

llvm-svn: 24081

llvm-svn: 24080

test for the formation of shladd

llvm-svn: 24077

change.

llvm-svn: 24076

llvm-svn: 24075

llvm-svn: 24074

llvm-svn: 24073