- Mar 27, 2007
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Evan Cheng authored
llvm-svn: 35366
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- Mar 26, 2007
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Bill Wendling authored
llvm-svn: 35353
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Bill Wendling authored
llvm-svn: 35352
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Bill Wendling authored
#include <mmintrin.h> extern __m64 C; void baz(__v2si *A, __v2si *B) { *A = C; _mm_empty(); } We get this: _baz: call "L1$pb" "L1$pb": popl %eax movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax movq (%eax), %mm0 movl 4(%esp), %eax movq %mm0, (%eax) emms ret GCC gives us this: _baz: pushl %ebx call L3 "L00000000001$pb": L3: popl %ebx subl $8, %esp movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax movl (%eax), %edx movl 4(%eax), %ecx movl 16(%esp), %eax movl %edx, (%eax) movl %ecx, 4(%eax) emms addl $8, %esp popl %ebx ret llvm-svn: 35351
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- Mar 25, 2007
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Anton Korobeynikov authored
llvm-svn: 35337
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Chris Lattner authored
llvm-svn: 35334
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Chris Lattner authored
llvm-svn: 35330
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Chris Lattner authored
llvm-svn: 35329
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Chris Lattner authored
not just the first letter. No functionality change. llvm-svn: 35322
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Chris Lattner authored
Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. llvm-svn: 35320
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Chris Lattner authored
llvm-svn: 35319
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Chris Lattner authored
llvm-svn: 35318
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- Mar 24, 2007
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Chris Lattner authored
llvm-svn: 35296
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Anton Korobeynikov authored
llvm-svn: 35292
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- Mar 23, 2007
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Bill Wendling authored
Add final support to get the QT example to compile. llvm-svn: 35290
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- Mar 22, 2007
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Bill Wendling authored
intrinsic. llvm-svn: 35269
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Bill Wendling authored
llvm-svn: 35266
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- Mar 21, 2007
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Dale Johannesen authored
llvm-svn: 35245
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Anton Korobeynikov authored
llvm-svn: 35244
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Anton Korobeynikov authored
llvm-svn: 35242
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Dale Johannesen authored
llvm-svn: 35241
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Nicolas Geoffray authored
is the frame pointer. llvm-svn: 35233
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Evan Cheng authored
llvm-svn: 35230
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- Mar 20, 2007
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Evan Cheng authored
llvm-svn: 35229
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Dale Johannesen authored
instructions (that would have to be split later) llvm-svn: 35227
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Lauro Ramos Venancio authored
mov lr, pc bx lr So, the function was not called. llvm-svn: 35218
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Evan Cheng authored
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. llvm-svn: 35207
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Evan Cheng authored
llvm-svn: 35206
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Evan Cheng authored
llvm-svn: 35205
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Chris Lattner authored
1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
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Chris Lattner authored
llvm-svn: 35202
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Dale Johannesen authored
llvm-svn: 35196
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- Mar 19, 2007
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Evan Cheng authored
llvm-svn: 35163
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Evan Cheng authored
rematerializable. Only used for constant generation for now. llvm-svn: 35162
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Evan Cheng authored
llvm-svn: 35161
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Evan Cheng authored
llvm-svn: 35160
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Chris Lattner authored
llvm-svn: 35152
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- Mar 18, 2007
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Chris Lattner authored
llvm-svn: 35143
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Nick Lewycky authored
entry: icmp ugt i32 %x, 4 ; <i1>:0 [#uses=1] br i1 %0, label %cond_true, label %cond_false cond_true: ; preds = %entry %tmp1 = tail call i32 (...)* @bar( i32 12 ) ; <i32> [#uses=0] ret void cond_false: ; preds = %entry switch i32 %x, label %cond_true15 [ i32 4, label %cond_true3 i32 3, label %cond_true7 i32 2, label %cond_true11 i32 0, label %cond_false17 ] ... llvm-svn: 35142
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- Mar 17, 2007
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Devang Patel authored
llvm-svn: 35129
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