rdar://problem/9224276

llvm-svn: 128749

rdar://problem/9224120

llvm-svn: 128748

block pointer nested inside a block. // rdar:// 9204669

llvm-svn: 128747

all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094

llvm-svn: 128746

llvm-svn: 128745

- Localize the check if an icmp has one use to a place where we know we're
  introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
  folded away earlier.
- Fix a typo.

llvm-svn: 128744

llvm-svn: 128743

Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.

llvm-svn: 128742

llvm-svn: 128741

llvm-svn: 128740

When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.

llvm-svn: 128739

llvm-svn: 128738

llvm-svn: 128736

llvm-svn: 128735

Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.

llvm-svn: 128734

llvm-svn: 128733

int test1(unsigned x) { return (x&8) ? 0 : -1; }
int test3(unsigned x) { return (x&8) ? -1 : 0; }

before (x86_64):
_test1:
	andl	$8, %edi
	cmpl	$1, %edi
	sbbl	%eax, %eax
	ret
_test3:
	andl	$8, %edi
	cmpl	$1, %edi
	sbbl	%eax, %eax
	notl	%eax
	ret

after:
_test1:
	shrl	$3, %edi
	andl	$1, %edi
	leal	-1(%rdi), %eax
	ret
_test3:
	shll	$28, %edi
	movl	%edi, %eax
	sarl	$31, %eax
	ret

llvm-svn: 128732

llvm-svn: 128731

llvm-svn: 128730

Assign node order numbers to results of call instruction lowering. This should improve src line debug info when sdisel is used. rdar://9199118

llvm-svn: 128728

with the contents of CMAKE_C(XX)_FLAGS too, else `llvm-config
--c(xx)flags' doesn't tell the absolute truth.

This comes from PR9603 and is based on a patch by Ryuta Suzuki!

llvm-svn: 128727

__byref block. // rdar://9204669

llvm-svn: 128726

llvm-svn: 128725

Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.

llvm-svn: 128724

llvm-svn: 128723

Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).

rdar://problem/9219356

llvm-svn: 128722

llvm-svn: 128721

respectively.

llvm-svn: 128720

Patch by arrowdoger.

llvm-svn: 128719

llvm-svn: 128718

llvm-svn: 128709

list of operands. Simplify and rename them accordingly.

llvm-svn: 128708

llvm-svn: 128707

llvm-svn: 128706

had gotten out of sync: isCastable didn't think it was possible to
cast the x86_mmx type to anything, while it did think it possible
to cast an i64 to x86_mmx.

llvm-svn: 128705

Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables.

llvm-svn: 128703

location into a TemplateSpecializationTypeLoc. These were found using
a hand-written program to inspect every source location in
TemplateSpecializationTypeLocs and Valgrind. I don't know of any way to
test them in Clang's existing test suite sadly.

Example code that triggers the ElaboratedType case:
  template <typename T> struct X1 {
    template <typename U> struct X1_1 {
      int x;
    };
  };

  template <typename T, typename U> struct X2 {
    typename X1<T>::template X1_1<U> B;
  };

  X2<char, int> x2;

The other fix was simply spotted by inspection. I audited all constructions of
[Dependent]TemplateSpecializationTypeLocs in TreeTransform.h, and the rest set
the TemplateNameLoc properly.

llvm-svn: 128702

llvm-svn: 128701

that of the array element type.

llvm-svn: 128698

llvm-svn: 128697