A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548

Thanks to Kristaps Straupe for noticing the bug.

llvm-svn: 95537

llvm-svn: 95506

- o32 cc must pass all arguments in A0...A3 and stack regardless
if its type (but respect the alignment).
- Store all variable arguments back to the caller stack.

llvm-svn: 95500

only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493

llvm-svn: 95477

Do not emit callseq instructions around sibcalls. This eliminated some unnecessary stack adjustments.

llvm-svn: 95475

This time it's for real! I am going to hook this up in the frontends as well.

The inliner has some experimental heuristics for dealing with the inline hint.
When given a -respect-inlinehint option, functions marked with the inline
keyword are given a threshold just above the default for -O3.

We need some experiments to determine if that is the right thing to do.

llvm-svn: 95466

Radar 7614112.

llvm-svn: 95456

llvm-svn: 95448

redundant with a correct one) pattern that was added for the disassembler.

llvm-svn: 95446

llvm-svn: 95445

llvm-svn: 95440

llvm-svn: 95438

llvm-svn: 95437

llvm-svn: 95435

pseudo instructions.

llvm-svn: 95433

llvm-svn: 95432

lower the SETB* instructions.

llvm-svn: 95431

llvm-svn: 95414

llvm-svn: 95410

llvm-svn: 95408

TSFlags directly instead of a TargetInstrDesc.

llvm-svn: 95405

llvm-svn: 95403

llvm-svn: 95397

llvm-svn: 95368

llvm-svn: 95351

to start limping.

llvm-svn: 95350

	pushl	%ebp
	movl	%esp, %ebp
	movl	$42, %eax
	popl	%ebp
	ret

llvm-svn: 95344

Instruction selection for X86 now can choose an instruction
sequence that will fit any address of any symbol, no matter
the pointer width. X86-64 uses a mov+call-via-reg sequence
for this.

llvm-svn: 95323

llvm-svn: 95299

llvm-svn: 95295

64-bit sparc codegen.  Patch by Nathan Keynes!

llvm-svn: 95293

Indirect tail call has to go through a call preserved register since it's after callee register pops. X86 isel lowering is using EAX / R11 and it was somehow adding that to function live out. That prevented the real function return register from being added to the function live out list and bad things happen.
This fixes 483.xalancbmk (with tail call opt).

llvm-svn: 95280

again, so it more or less handles long double.
Restore \n removed in latest MC frenzy.

llvm-svn: 95271

instructions with no operands.  It can now handle

define void @test2() nounwind { ret void }

llvm-svn: 95261

llvm-svn: 95260

Speculatively disable x86 automatic tail call optimization while we track down a self-hosting issue.

llvm-svn: 95259

-enable-new-x86-encoder until its stable.

llvm-svn: 95256

llvm-svn: 95254