llvm-svn: 125420

Don't emit a dead store for '++' operations unless it occurs with a return statement.  We've never seen any other cases that were real bugs.

Fixes <rdar://problem/6962292>.

llvm-svn: 125419

llvm-svn: 125418

I also sorted the tools/driver dependencies since their order no
longer matters.

llvm-svn: 125417

llvm-svn: 125416

llvm-svn: 125415

- Add three more instruction contexts to EmulateInstruction:
eContextAdjustBaseRegister, eContextRegisterStore and
eContextWriteMemoryRandomBits.

- Implement a version of WriteBits32UnknownToMemory for writing to memory.

- Modify EmulateLDM, EmulateLDMDA, EmulateLDMDB and EmulateLDMIB to use the
eContextAdjustBaseRegister context when appropriate.

- Add code to emulate the STM/STMIA/STMEA Arm instruction.

llvm-svn: 125414

CMP (register) operations.

llvm-svn: 125413

llvm-svn: 125412

llvm-svn: 125411

unsigned overflow (e.g. "gep P, -1"), and while they can have
signed wrap in theoretical situations, modelling an AddRec as
not having signed wrap is going enough for any case we can 
think of today.  In the future if this isn't enough, we can
revisit this.  Modeling them as having NUW isn't causing any
known problems either FWIW.

llvm-svn: 125410

unsigned overflow (e.g. due to a negative array index), but
the scales on array size multiplications are known to not
sign wrap.

llvm-svn: 125409

llvm-svn: 125408

Reviewed by dgregor.

llvm-svn: 125407

on the host OS.  Reviewed by dgregor.

llvm-svn: 125406

llvm-svn: 125405

This avoids moving each element to the integer register file and calling __divsi3 etc. on it.

llvm-svn: 125402

llvm-svn: 125401

checks that the process is stopped due to breakpoint at the specified line no.

llvm-svn: 125400

llvm-svn: 125399

that the condition is not a vector.

llvm-svn: 125398

llvm-svn: 125396

llvm-svn: 125395

Rename the operation that loads a preprocessed entity from a given offset to indicate that we're loading from an offset, not an index, lest one be confused. No functionality change.

llvm-svn: 125394

Add more folding patterns to constant expressions of vector selects and vector
bitcasts.

llvm-svn: 125393

llvm-svn: 125392

Fix #9190

The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.

llvm-svn: 125391

Change the method name from *LDRRdPCRelative to *LDRRtPCRelative to be compliant
with the ARM Arch Manual which uses Rt for the destination register.

llvm-svn: 125390

llvm-svn: 125389

llvm-svn: 125388

is unqualified but its initialized is qualified.
This is for c only and fixes the imm. problem.
c++ is more involved and is wip.
// rdar://8979379

llvm-svn: 125386

llvm-svn: 125385

This patch contains:

- making some of the existing comments more accurate in the presence
of virtual files/directories.

- renaming some private data members of FileManager to match their roles better.

- creating 'DirectorEntry's for the parent directories of virtual
files, such that we can tell whether two virtual files are from the
same directory.  This is useful for injecting virtual files whose
directories don't exist in the real file system.

- minor clean-ups and adding comments for class
FileManager::UniqueDirContainer and FileManager::UniqueFileContainer.

- adding statistics on virtual files to FileManager::PrintStats().

- adding unit tests to verify the existing and new behavior of FileManager.

llvm-svn: 125384

objects, since they'll end up using the implicit conversion to "bool"
and causing some very "fun" surprises.

llvm-svn: 125380

llvm-svn: 125379

contents when it's safe. I just *love* C++ some days.

llvm-svn: 125378

Add new utility function, WriteBits32Unknown

Modify the LDM* instruction emulation functions to call WriteBits32Unknown.
Add missing overview comments to the LDM* instruction emulation functions.

Add code to emulate LDMDA Arm instruction.

llvm-svn: 125377

a loop when unswitching it. It only does this in the complex case, because
everything should be fine already in the simple case.

llvm-svn: 125369

llvm-svn: 125368

llvm-svn: 125367